公开(公告)号：US11049767B2

公开(公告)日：2021-06-29

申请号：US16584594

申请日：2019-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsai-Ming Huang ,  Wei-Chieh Huang ,  Hsun-Chung Kuang ,  Yen-Chang Chu ,  Cheng-Che Chung ,  Chin-Wei Liang ,  Ching-Sen Kuo ,  Jieh-Jang Chen ,  Feng-Jia Shiu ,  Sheng-Chau Chen

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L23/544 ,  H01L23/522

摘要： In a method of manufacturing a semiconductor device, a first interlayer dielectric (ILD) layer is formed over a substrate, a chemical mechanical polishing (CMP) stop layer is formed over the first ILD layer, a trench is formed by patterning the CMP stop layer and the first ILD layer, a metal layer is formed over the CMP stop layer and in the trench, a sacrificial layer is formed over the metal layer, a CMP operation is performed on the sacrificial layer and the metal layer to remove a portion of the metal layer over the CMP stop layer, and a remaining portion of the sacrificial layer over the trench is removed.

公开(公告)号：US10943783B2

公开(公告)日：2021-03-09

申请号：US16427299

申请日：2019-05-30

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Che Chung ,  Yi Jen Tsai ,  Ching-Sen Kuo ,  Tsai-Ming Huang ,  Jieh-Jang Chen ,  Feng-Jia Shiu

IPC分类号： H01L21/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/768 ,  G03F7/32 ,  H01L21/3105

摘要： In a method of manufacturing a semiconductor device, a first layer having an opening is formed over a substrate. A second layer is formed over the first layer and the substrate. A photo resist pattern is formed over the second layer above the opening of the first layer. The photo resist pattern is reflowed by a thermal process. An etch-back operation is performed to planarize the second layer.

公开(公告)号：US09026956B1

公开(公告)日：2015-05-05

申请号：US14051640

申请日：2013-10-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Cheng Chang ,  Wei-Kuan Yu ,  Tsai-Ming Huang ,  Chin-Min Huang ,  Cherng-Shyan Tsay ,  Chien Wen Lai ,  Hua-Tai Lin ,  Shih-Ming Chang

IPC分类号： G06F17/50

CPC分类号： G03F7/705 ,  G03F7/70441

摘要： Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

摘要翻译： 本公开的一些实施例涉及一种模拟布局图案化的方法。 该方法包括在第一光刻条件下模拟布局图案的形成。 第一光刻条件包括一组参数，其中每个参数的值由相应的过程模型定义。 该方法还包括在由参数的相应过程模型定义的值的范围内随机地改变第一光刻条件的每个参数的值，以产生第二光刻条件。 然后在第二光刻条件下重新模拟布局图案的形成。 重复每个参数的值的随机变化以产生另外的光刻条件。 并且，每个光刻条件被重新模拟，直到每个参数的值在其各自的处理模型的范围内已经基本上变化。

公开(公告)号：US20150106771A1

公开(公告)日：2015-04-16

申请号：US14051640

申请日：2013-10-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Cheng Chang ,  Wei-Kuan Yu ,  Tsai-Ming Huang ,  Chin-Min Huang ,  Cherng-Shyan Tsay ,  Chien Wen Lai ,  Hua-Tai Lin ,  Shih-Ming Chang

IPC分类号： G06F17/50

CPC分类号： G03F7/705 ,  G03F7/70441

摘要： Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

摘要翻译： 本公开的一些实施例涉及一种模拟布局图案化的方法。 该方法包括在第一光刻条件下模拟布局图案的形成。 第一光刻条件包括一组参数，其中每个参数的值由相应的过程模型定义。 该方法还包括在由参数的相应过程模型定义的值的范围内随机地改变第一光刻条件的每个参数的值，以产生第二光刻条件。 然后在第二光刻条件下重新模拟布局图案的形成。 重复每个参数的值的随机变化以产生另外的光刻条件。 并且，每个光刻条件被重新模拟，直到每个参数的值在其各自的处理模型的范围内已经基本上变化。