公开(公告)号：US08972909B1

公开(公告)日：2015-03-03

申请号：US14038943

申请日：2013-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chang ,  Jau-Shian Liang ,  Wen-Chen Lu ,  Chin-Min Huang ,  Ming-Hui Chih ,  Cherng-Shyan Tsay ,  Chien-Wen Lai ,  Hua-Tai Lin

IPC: G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

CPC classification number: G03F7/70441 ,  G03F1/00 ,  G03F1/36 ,  G06F17/5072 ,  G06F19/00 ,  G06F2217/12 ,  G06F2217/14 ,  G21K5/00

Abstract: The present disclosure relates to a method of performing an optical proximity correction (OPC) procedure that provides for a high degree of freedom by using an approximation design layer. In some embodiments, the method is performed by forming an integrated chip (IC) design having an original design layer with one or more original design shapes. An approximation design layer, which is different from the original design layer, is generated from the original design layer. The approximation design layer is a design layer that has been adjusted to remove features that may cause optical proximity correction (OPC) problems. An optical proximity correction (OPC) procedure is then performed on the approximation design layer. By performing the OPC procedure on the approximation design layer rather than on the original design layer, characteristics of the OPC procedure can be improved.

Abstract translation: 本公开涉及一种执行通过使用近似设计层提供高自由度的光学邻近校正（OPC）过程的方法。 在一些实施例中，该方法通过形成具有一个或多个原始设计形状的原始设计层的集成芯片（IC）设计来执行。 从原始设计层产生与原始设计层不同的近似设计层。 近似设计层是已经被调整以去除可能引起光学邻近校正（OPC）问题的特征的设计层。 然后在近似设计层上执行光学邻近校正（OPC）过程。 通过在近似设计层而不是原始设计层上执行OPC程序，可以提高OPC程序的特性。

公开(公告)号：US20150082265A1

公开(公告)日：2015-03-19

申请号：US14029902

申请日：2013-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Min Huang ,  Chia-Cheng Chang ,  Cherng-Shyan Tsay ,  Chien-Wen Lai ,  Kong-Beng Thei ,  Hua-Tai Lin ,  Hung-Chang Hsieh

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  H01L21/76895 ,  H01L23/528

Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.

Abstract translation: 一个实施例涉及一种实现大于照明工具的曝光场的尺寸的电路尺寸的方法。 定义第一掩模版场的第一区域和第二掩模版场的第二区域。 创建延伸区域作为第一区域外的区域，并且包括形成在第一设计级上的第一布局形状。 为第二标线区域创建相应的禁止区域作为第一区域内的区域，其中不允许第一设计层面上的布局形状。 在禁区内的第二设计级上形成第二布局形状。 然后将第一和第二区域邻接。 在第一和第二区域邻接时，第二布局形状与第一布局形状重叠以形成第一和第二掩模版区域的电路之间的连接。

公开(公告)号：US08972912B1

公开(公告)日：2015-03-03

申请号：US14029902

申请日：2013-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Min Huang ,  Chia-Cheng Chang ,  Cherng-Shyan Tsay ,  Chien-Wen Lai ,  Kong-Beng Thei ,  Hua-Tai Lin ,  Hung-Chang Hsieh

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  H01L21/76895 ,  H01L23/528

Abstract: One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields.

Abstract translation: 一个实施例涉及一种实现大于照明工具的曝光场的尺寸的电路尺寸的方法。 定义第一掩模版场的第一区域和第二掩模版场的第二区域。 创建延伸区域作为第一区域外的区域，并且包括形成在第一设计级上的第一布局形状。 为第二标线区域创建相应的禁止区域作为第一区域内的区域，其中不允许第一设计层面上的布局形状。 在禁区内的第二设计级上形成第二布局形状。 然后将第一和第二区域邻接。 在第一和第二区域邻接时，第二布局形状与第一布局形状重叠以形成第一和第二掩模版区域的电路之间的连接。

公开(公告)号：US11621191B2

公开(公告)日：2023-04-04

申请号：US17135758

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yuan-Yen Lo ,  Chia-Cheng Chang ,  Ming-Jhih Kuo ,  Chien-Yuan Chen

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/32

Abstract: In a method of manufacturing a semiconductor device, initial connection patterns are prepared, initial cutting patterns for cutting the initial connection patterns are prepared, non-functional connection patterns at least from the initial connection patterns are identified, final cutting patterns are prepared from the initial cutting patterns and the non-functional connection patterns, a photo mask is prepared from the final cutting patterns, a photo resist pattern is formed over a target layer by a lithography operation using the photo mask, the target layer is patterned to form openings in the target layer by using the photo resist pattern, and connection layers are formed by filling the openings with a conductive material.

公开(公告)号：US09026956B1

公开(公告)日：2015-05-05

申请号：US14051640

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chang ,  Wei-Kuan Yu ,  Tsai-Ming Huang ,  Chin-Min Huang ,  Cherng-Shyan Tsay ,  Chien Wen Lai ,  Hua-Tai Lin ,  Shih-Ming Chang

IPC: G06F17/50

CPC classification number: G03F7/705 ,  G03F7/70441

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract translation: 本公开的一些实施例涉及一种模拟布局图案化的方法。 该方法包括在第一光刻条件下模拟布局图案的形成。 第一光刻条件包括一组参数，其中每个参数的值由相应的过程模型定义。 该方法还包括在由参数的相应过程模型定义的值的范围内随机地改变第一光刻条件的每个参数的值，以产生第二光刻条件。 然后在第二光刻条件下重新模拟布局图案的形成。 重复每个参数的值的随机变化以产生另外的光刻条件。 并且，每个光刻条件被重新模拟，直到每个参数的值在其各自的处理模型的范围内已经基本上变化。

公开(公告)号：US20150106771A1

公开(公告)日：2015-04-16

申请号：US14051640

申请日：2013-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Cheng Chang ,  Wei-Kuan Yu ,  Tsai-Ming Huang ,  Chin-Min Huang ,  Cherng-Shyan Tsay ,  Chien Wen Lai ,  Hua-Tai Lin ,  Shih-Ming Chang

IPC: G06F17/50

CPC classification number: G03F7/705 ,  G03F7/70441

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract translation: 本公开的一些实施例涉及一种模拟布局图案化的方法。 该方法包括在第一光刻条件下模拟布局图案的形成。 第一光刻条件包括一组参数，其中每个参数的值由相应的过程模型定义。 该方法还包括在由参数的相应过程模型定义的值的范围内随机地改变第一光刻条件的每个参数的值，以产生第二光刻条件。 然后在第二光刻条件下重新模拟布局图案的形成。 重复每个参数的值的随机变化以产生另外的光刻条件。 并且，每个光刻条件被重新模拟，直到每个参数的值在其各自的处理模型的范围内已经基本上变化。

公开(公告)号：US08952329B1

公开(公告)日：2015-02-10

申请号：US14045138

申请日：2013-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Chang Shih ,  Yi-Jie Chen ,  Chia-Cheng Chang ,  Feng-Yuan Chiu ,  Ying-Chou Cheng ,  Chiu Hsiu Chen ,  Bing-Syun Yeh ,  Ru-Gun Liu

IPC: G01N23/00 ,  G21K7/00 ,  G01B15/04

CPC classification number: H01L22/12 ,  G01B2210/56 ,  G03F7/70433 ,  G03F7/705

Abstract: A method for characterizing a three-dimensional surface profile of a semiconductor workpiece is provided. In this method, the three-dimensional surface profile is imaged from a normal angle to measure widths of various surfaces in a first image. The three-dimensional surface is also imaged from a first oblique angle to re-measure the widths of the various surfaces in a second image. Based on differences in widths of corresponding surfaces for first and second images, a feature height and sidewall angle are determined for the three-dimensional profile.

Abstract translation: 提供了一种用于表征半导体工件的三维表面轮廓的方法。 在该方法中，从正常角度对三维表面轮廓进行成像，以测量第一图像中的各种表面的宽度。 三维表面也从第一倾斜角度成像，以重新测量第二图像中各种表面的宽度。 基于第一和第二图像的相应表面的宽度差异，确定三维轮廓的特征高度和侧壁角度。