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公开(公告)号：US10609463B2
公开(公告)日：2020-03-31
申请号：US15797813
申请日：2017-10-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Wen-Cheng Kuo , Chia-Hua Chu , Chun-Yin Tsai , Tzu-Heng Wu
Abstract: An integrated microphone device is provided. The integrated microphone device includes a substrate, a plate, and a membrane. The substrate includes an aperture allowing acoustic pressure to pass through. The plate is disposed on a side of the substrate. The membrane is disposed between the substrate and the plate and movable relative to the plate as acoustic pressure strikes the membrane. The membrane includes a vent valve having an open area that is variable in response to a change in acoustic pressure.
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公开(公告)号：US20160145095A1
公开(公告)日：2016-05-26
申请号：US14639530
申请日：2015-03-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Heng Tsai , Yi-Hsien Chang , Chun-Ren Cheng , Chun-Wen Cheng , Tzu-Heng Wu , Wei-Cheng Shen
CPC classification number: B81C1/00238 , B81B7/0048
Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.
Abstract translation: 三维（3D）集成电路（IC）包括第一IC和第二IC。 第一IC包括MEMS器件和第一接合结构。 第二IC包括第二接合结构。 第一和第二接合结构被结合在一起以将第一IC耦合到第二IC。 在距离第一IC最近的第二IC的表面上设置保形阻挡层。 蚀刻隔离结构被布置在第二IC的表面下方并且包围一个牺牲区域，该牺牲区域被布置在第二接合结构的任一侧上并且被布置在第二IC中。
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公开(公告)号：US09493346B2
公开(公告)日：2016-11-15
申请号：US14445226
申请日：2014-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Shen , Yi-Hsien Chang , Yi Heng Tsai , Tzu-Heng Wu , Chun-Ren Cheng , Chun-Wen Cheng
CPC classification number: B81C1/00238
Abstract: An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.
Abstract translation: 提供集成电路（IC）结构。 IC结构包括IC基板，其包括通过布置在其上的导电互连结构耦合在一起的有源器件。 导电互连结构包括布置在相邻的水平导电层之间的一系列水平导电层和电介质区域。 导电互连结构包括具有平坦顶表面区域的最上面的导电水平区域。 MEMS基板布置在IC基板上方，并且包括柔性或可移动的结构，其以施加到柔性或可移动结构的力相应地弯曲或移动。 IC基板的有源器件被布置成建立分析电路，以便于电测量最上面的导电水平区域和柔性或可移动结构之间的电容。
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公开(公告)号：US09449867B2
公开(公告)日：2016-09-20
申请号：US14306643
申请日：2014-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Heng Wu , Yi-Hsien Chang , Kai-Chih Liang , Yi Heng Tsai , Wei-Cheng Shen , Chun-Ren Cheng , Chun-Wen Cheng , Han-Chin Chiu
IPC: B81C3/00 , B81B7/00 , H01L21/762 , H01L23/00 , H01L27/092
CPC classification number: H01L21/76232 , B81B7/0025 , B81B7/0054 , B81B7/008 , B81C1/00238 , B81C1/00801 , B81C3/001 , H01L24/89 , H01L27/092
Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.
Abstract translation: 本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。 在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF） 死。 第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。
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5.发明申请VHF ETCH BARRIER FOR SEMICONDUCTOR INTEGRATED MICROSYSTEM 有权用于SEMICONDUCTOR INTEGRATED MICROSYSTEM的VHF ETCH BARRIER公开(公告)号：US20150364363A1
公开(公告)日：2015-12-17
申请号：US14306643
申请日：2014-06-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Heng Wu , Yi-Hsien Chang , Kai-Chih Liang , Yi Heng Tsai , Wei-Cheng Shen , Chun-Ren Cheng , Chun-Wen Cheng , Han-Chin Chiu
IPC: H01L21/762 , B81C3/00 , B81B7/00 , H01L27/092 , H01L23/00
CPC classification number: H01L21/76232 , B81B7/0025 , B81B7/0054 , B81B7/008 , B81C1/00238 , B81C1/00801 , B81C3/001 , H01L24/89 , H01L27/092
Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.
Abstract translation: 本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。 在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF） 死。 第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。
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Patent Agency Ranking
公开(公告)号：US11097941B2
公开(公告)日：2021-08-24
申请号：US16398013
申请日：2019-04-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Hsien Chang , Tzu-Heng Wu , Chun-Ren Cheng , Shih-Wei Lin , Jung-Kuo Tu
IPC: B81B3/00
Abstract: A method includes forming a recess in a first substrate, bonding a micro-electro-mechanical systems (MEMS) substrate to the first substrate after forming the recess in the first substrate, forming an anti-stiction layer over the micro-electro-mechanical systems (MEMS) substrate, pattering the anti-stiction layer, etching the MEMS substrate to form a MEMS device, and bonding the MEMS device and the first substrate to a second substrate. The patterned anti-stiction layer is between the MEMS device and the second substrate.
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公开(公告)号：US20160031704A1
公开(公告)日：2016-02-04
申请号：US14445226
申请日：2014-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Wei-Cheng Shen , Yi-Hsien Chang , Yi Heng Tsai , Tzu-Heng Wu , Chun-Ren Cheng , Chun-Wen Cheng
CPC classification number: B81C1/00238
Abstract: An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.
Abstract translation: 提供集成电路（IC）结构。 IC结构包括IC基板，其包括通过布置在其上的导电互连结构耦合在一起的有源器件。 导电互连结构包括布置在相邻的水平导电层之间的一系列水平导电层和电介质区域。 导电互连结构包括具有平坦顶表面区域的最上面的导电水平区域。 MEMS基板布置在IC基板上方，并且包括柔性或可移动的结构，其以施加到柔性或可移动结构的力相应地弯曲或移动。 IC基板的有源器件被布置成建立分析电路，以便于电测量最上面的导电水平区域和柔性或可移动结构之间的电容。
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公开(公告)号：US11184694B2
公开(公告)日：2021-11-23
申请号：US16813923
申请日：2020-03-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Chia-Hua Chu , Chun-Yin Tsai , Tzu-Heng Wu , Wen-Cheng Kuo
Abstract: An integrated microphone device is provided. The integrated microphone device includes a substrate, a plate, and a membrane. The substrate includes an aperture allowing acoustic pressure to pass through. The plate is disposed on a side of the substrate. The membrane is disposed between the substrate and the plate and movable relative to the plate as acoustic pressure strikes the membrane. The membrane includes a vent valve having an open area that is variable in response to a change in acoustic pressure.
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公开(公告)号：US10273140B2
公开(公告)日：2019-04-30
申请号：US14599218
申请日：2015-01-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Hsien Chang , Tzu-Heng Wu , Chun-Ren Cheng , Shih-Wei Lin , Jung-Kuo Tu
Abstract: A substrate structure for a micro electro mechanical system (MEMS) device, a semiconductor structure and a method for fabricating the same are provided. In various embodiments, the substrate structure for the MEMS device includes a substrate, the MEMS device, and an anti-stiction layer. The MEMS device is over the substrate. The anti-stiction layer is on a surface of the MEMS device, and includes amorphous carbon, polytetrafluoroethene, hafnium oxide, tantalum oxide, zirconium oxide, or a combination thereof.
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公开(公告)号：US09446945B2
公开(公告)日：2016-09-20
申请号：US14639530
申请日：2015-03-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Heng Tsai , Yi-Hsien Chang , Chun-Ren Cheng , Chun-Wen Cheng , Tzu-Heng Wu , Wei-Cheng Shen
IPC: H01L31/0203 , B81B7/00 , B81C1/00
CPC classification number: B81C1/00238 , B81B7/0048
Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC and a second IC. The first IC includes a MEMS device and a first bonding structure. The second IC includes a second bonding structure. The first and second bonding structures are bonded together to couple the first IC to the second IC. A conformal barrier layer is disposed over a surface of the second IC nearest the first IC. An etch isolation structure is arranged beneath the surface of the second IC and encloses a sacrificial region which is arranged on either side of the second bonding structure and which is arranged in the second IC.
Abstract translation: 三维（3D）集成电路（IC）包括第一IC和第二IC。 第一IC包括MEMS器件和第一接合结构。 第二IC包括第二接合结构。 第一和第二接合结构被结合在一起以将第一IC耦合到第二IC。 在距离第一IC最近的第二IC的表面上设置保形阻挡层。 蚀刻隔离结构被布置在第二IC的表面下方并且包围一个牺牲区域，该牺牲区域被布置在第二接合结构的任一侧上并且被布置在第二IC中。
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