公开(公告)号：US09799644B2

公开(公告)日：2017-10-24

申请号：US14746893

申请日：2015-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yi Yang ,  Kuo-Ji Chen ,  Chien-Yuan Lee

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/0288 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.

公开(公告)号：US20150171074A1

公开(公告)日：2015-06-18

申请号：US14106936

申请日：2013-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yi Yang ,  Kuo-Ji Chen ,  Chien-Yuan Lee

IPC: H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0288 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.

Abstract translation: FinFET器件包括形成在多电平互连半导体器件中的对应的多个鳍片上的多个FinFET器件。 每个源极和每个漏极通过位于最低互连电平以下的金属电阻元件耦合到金属互连电平。 在一个实施例中，在多个翅片上延伸的金属段包括到每个翅片的触点，从而提供不同长度的下面的金属电阻元件。 多个翅片和下面的金属段被布置成使得每个FinFET器件具有由源极和漏极金属电阻元件提供的相同的总电阻，即使与鳍片相关联的源极金属电阻元件和漏极金属电阻元件可具有 不同长度 该布置为每个FinFET器件提供相同的导通电阻和相同的ESD故障电流。

公开(公告)号：US09082623B2

公开(公告)日：2015-07-14

申请号：US14106936

申请日：2013-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yi Yang ,  Kuo-Ji Chen ,  Chien-Yuan Lee

IPC: H01L29/76 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L27/0288 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.

Abstract translation: FinFET器件包括形成在多电平互连半导体器件中的对应的多个鳍片上的多个FinFET器件。 每个源极和每个漏极通过位于最低互连电平以下的金属电阻元件耦合到金属互连电平。 在一个实施例中，在多个翅片上延伸的金属段包括到每个翅片的触点，从而提供不同长度的下面的金属电阻元件。 多个翅片和下面的金属段被布置成使得每个FinFET器件具有由源极和漏极金属电阻元件提供的相同的总电阻，即使与鳍片相关联的源极金属电阻元件和漏极金属电阻元件可具有 不同长度 该布置为每个FinFET器件提供相同的导通电阻和相同的ESD故障电流。