公开(公告)号：US20250142950A1

公开(公告)日：2025-05-01

申请号：US19004755

申请日：2024-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

IPC: H10D84/83 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10 ,  H10D84/80

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

公开(公告)号：US12176341B2

公开(公告)日：2024-12-24

申请号：US18513544

申请日：2023-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L27/02 ,  H02H9/04

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: an internal circuit patterned in a device wafer and electrically coupled between a first node and a second node, an array of electrostatic discharge (ESD) circuits patterned in a carrier wafer, where the ESD circuits are electrically coupled between a first node and a second node and configured to protect the internal circuit from transient ESD events, and where the device wafer is bonded to the carrier wafer.

公开(公告)号：US11735587B2

公开(公告)日：2023-08-22

申请号：US17510014

申请日：2021-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L27/07 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0727 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

公开(公告)号：US11569223B2

公开(公告)日：2023-01-31

申请号：US17086076

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen ,  Chia-En Huang

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092

Abstract: A method for fabricating an integrated circuit is provided. The method includes etching a first recess in a semiconductor structure; forming a first doped epitaxial feature in the first recess; and forming a second doped epitaxial feature over the first doped epitaxial feature, wherein the second doped epitaxial feature has a conductive type opposite to a conductive type of the first doped epitaxial feature.

公开(公告)号：US11562996B2

公开(公告)日：2023-01-24

申请号：US16987292

申请日：2020-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Heng Chang ,  Kuo-Ji Chen ,  Ming-Hsiang Song

IPC: H01L27/02 ,  H01L27/088

Abstract: A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.

公开(公告)号：US20210175707A1

公开(公告)日：2021-06-10

申请号：US17180345

申请日：2021-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hung Chen ,  Kuo-Ji Chen ,  Shao-Yu Chou

IPC: H02H9/04 ,  H01L27/02 ,  H03K17/082

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

公开(公告)号：US10991663B2

公开(公告)日：2021-04-27

申请号：US16714542

申请日：2019-12-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yu Ma ,  Hui-Mei Chou ,  Kuo-Ji Chen

IPC: H01L21/4763 ,  H01L23/58 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

Abstract: A method is disclosed and includes forming a plurality of dummy conductive cells that provides different densities in empty areas in metal layers of a semiconductor device according to overlap conditions of the empty areas each arranged between a pair of neighboring metal layers of metal layers. Forming the plurality of dummy conductive cells includes operations of forming a group of dummy conductive cells in a single empty area of the empty areas when the single empty area in one pair of the neighboring metal layers is overlapped by a signal line in the same pair of the neighboring metal layers. When viewed in plan view, projection areas of the group of dummy conductive cells are vertically overlapped by a projection area of the signal line. A semiconductor device is also disclosed herein.

公开(公告)号：US09799644B2

公开(公告)日：2017-10-24

申请号：US14746893

申请日：2015-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yi Yang ,  Kuo-Ji Chen ,  Chien-Yuan Lee

IPC: H01L27/02 ,  H01L27/088 ,  H01L27/06 ,  H01L23/528 ,  H01L49/02 ,  H01L29/78

CPC classification number: H01L27/0288 ,  H01L23/528 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A FinFET device includes a plurality of FinFET devices formed on a corresponding plurality of fins in a multilevel interconnect semiconductor device. Each source and each drain is coupled to a metal interconnect level by a metal resistive element that is subjacent the lowermost interconnect level. In one embodiment, a metal segment extending over a plurality of the fins includes contacts to each of the fins, thereby providing subjacent metal resistive elements of different lengths. The plurality of fins and subjacent metal segments are arranged such that each of the FinFET devices has the same total resistance provided by the source and drain metal resistive elements, even though the source metal resistive element and drain metal resistive element associated with the fins may have different lengths. The arrangement provides the same turn-on resistance and the same ESD failure current for each FinFET device.

公开(公告)号：US20220302699A1

公开(公告)日：2022-09-22

申请号：US17837948

申请日：2022-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hung CHEN ,  Kuo-Ji Chen ,  Shao-Yu Chou

IPC: H02H9/04 ,  H03K17/082 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) circuit includes: a cascade of NMOS transistors including a first NMOS transistor operatively cascaded to a second NMOS transistor wherein the cascade of NMOS transistors is operatively coupled to a first bus that receives an ESD pulse signal; a first single-gate-oxide ESD control circuit coupled to the first NMOS transistor and configured to turn on the first NMOS transistor during an ESD event, the first single-gate-oxide control circuit coupled between the first bus at a first voltage and a first node at a second voltage, wherein the first voltage is higher than the second voltage; a second single-gate-oxide control circuit operatively coupled to the second NMOS transistor and configured to turn on the second NMOS transistor during an ESD event and to turn off the second NMOS transistor during a normal operation, wherein the second single-gate-oxide control circuit is coupled between the first node at the second voltage and a second bus at a ground voltage, wherein the second voltage is higher than the ground voltage; and a voltage divider circuit operatively coupled to the first bus at the first voltage and the second bus at the ground voltage, wherein the voltage divider circuit is operatively coupled to the first single-gate-oxide ESD control circuit and the second single-gate-oxide ESD control circuit at the first node.

公开(公告)号：US20220293534A1

公开(公告)日：2022-09-15

申请号：US17199299

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tao-Yi Hung ,  Wun-Jie Lin ,  Jam-Wem Lee ,  Kuo-Ji Chen

IPC: H01L23/60 ,  H02H9/04 ,  H01L27/02

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.