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    Voltage-controlled oscillator
    1.
    发明授权
    Voltage-controlled oscillator 有权
    压控振荡器

    公开(公告)号：US08937512B1

    公开(公告)日：2015-01-20

    申请号：US14062847

    申请日：2013-10-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Jr Huang ,  Nan-Hsin Tseng ,  Wei-Hao Kao ,  Ping-Han Tsai ,  Wei-Pin Changchien

    IPC: H03K3/03 ,  H03B28/00

    CPC classification number: H03K3/0315

    Abstract: A voltage-controlled oscillator is disclosed. The voltage-controlled oscillator includes an inverter circuit configured to output an oscillation signal. The first inverter circuit includes a complementary transistor pair and a transistor string. The complementary transistor pair includes a first switch transistor and a second switch transistor. The second switch transistor is connected to the first switch transistor, in which a first terminal of the second switch transistor is connected to a second terminal of the first switch transistor. The first delaying unit includes at least one delaying transistor. A first terminal of the at least one delaying transistor is connected to a control terminal of the second switch transistor. A second terminal of the at least one delaying transistor is connected to a control terminal of the first switch transistor. A control terminal of the at least one delaying transistor is configured to receive a voltage control signal.

    Abstract translation: 公开了压控振荡器。 压控振荡器包括被配置为输出振荡信号的反相器电路。 第一反相器电路包括互补晶体管对和晶体管串。 互补晶体管对包括第一开关晶体管和第二开关晶体管。 第二开关晶体管连接到第一开关晶体管，其中第二开关晶体管的第一端子连接到第一开关晶体管的第二端子。 第一延迟单元包括至少一个延迟晶体管。 所述至少一个延迟晶体管的第一端子连接到所述第二开关晶体管的控制端子。 所述至少一个延迟晶体管的第二端子连接到所述第一开关晶体管的控制端子。 所述至少一个延迟晶体管的控制端被配置为接收电压控制信号。

    Machine-learning design enablement platform
    2.
    发明授权
    Machine-learning design enablement platform 有权

    公开(公告)号：US11017149B2

    公开(公告)日：2021-05-25

    申请号：US16871841

    申请日：2020-05-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Lin Chuang ,  Ching-Fang Chen ,  Wei-Li Chen ,  Wei-Pin Changchien ,  Yung-Chin Hou ,  Yun-Han Lee

    IPC: G06F30/398 ,  G06N20/00 ,  G06F30/30 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373 ,  H01L27/02 ,  H05K3/00 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118 ,  G06F30/367 ,  G06F111/06 ,  G06F111/02 ,  G06F119/22

    Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

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