公开(公告)号：US11017149B2

公开(公告)日：2021-05-25

申请号：US16871841

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Ching-Fang Chen ,  Wei-Li Chen ,  Wei-Pin Changchien ,  Yung-Chin Hou ,  Yun-Han Lee

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/30 ,  G06F30/27 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373 ,  H01L27/02 ,  H05K3/00 ,  G06F30/392 ,  G06F30/394 ,  H01L27/118 ,  G06F30/367 ,  G06F111/06 ,  G06F111/02 ,  G06F119/22

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

公开(公告)号：US20160111511A1

公开(公告)日：2016-04-21

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09245974B2

公开(公告)日：2016-01-26

申请号：US14187850

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract translation: 本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。 外延层改善晶体管器件的性能。 在一些实施例中，通过提供半导体衬底来执行该方法。 进行外延生长以在半导体衬底上形成外延层。 然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。 通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09099324B2

公开(公告)日：2015-08-04

申请号：US14062838

申请日：2013-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

Abstract translation: 半导体器件包括半导体衬底和沟槽隔离。 沟槽隔离位于半导体衬底中，并且包括外延层和电介质材料。 外延层位于半导体的沟槽中并由其周边封闭，其中通过进行蚀刻和外延工艺形成外延层。 蚀刻和外延工艺包括蚀刻沟槽的侧壁的一部分和沟槽的底表面的一部分，并且形成与侧壁的剩余部分和底表面的剩余部分共形的外延层。 电介质材料由外延层周边封闭。

公开(公告)号：US11183262B2

公开(公告)日：2021-11-23

申请号：US16851107

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Ruei Li ,  Fan-Ming Kuo ,  Wei-Li Chen

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C29/56 ,  G11C29/46

Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

公开(公告)号：US10678973B2

公开(公告)日：2020-06-09

申请号：US15724663

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Ching-Fang Chen ,  Wei-Li Chen ,  Wei-Pin Changchien ,  Yung-Chin Hou ,  Yun-Han Lee

IPC: G06F17/50 ,  G06N20/00 ,  H01L27/00 ,  G06F30/27 ,  G06F30/30 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373 ,  H01L27/02 ,  H05K3/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  H01L27/118 ,  G06F30/367 ,  G06F111/06 ,  G06F111/02 ,  G06F119/22

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

公开(公告)号：US10038000B2

公开(公告)日：2018-07-31

申请号：US14857362

申请日：2015-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi Wu ,  Jian-Shin Tsai ,  Kuo-Hsien Cheng ,  Min-Hui Lin ,  Wei-Li Chen ,  Chao-Ching Chang ,  Chung-Yu Hsieh ,  Chin-Szu Lee

IPC: H01L27/112 ,  H01L23/525

CPC classification number: H01L27/11206 ,  H01L23/5252

Abstract: A memory cell includes a selector, a fuse connected to the selector in series, a contact etch stop layer formed on the selector and the fuse, a bit line connected to the fuse, and a word line connected to the selector. The contact etch stop layer includes a high-k dielectric for improving the ability of capturing the electrons, thus the retention time of the memory cell is increased.

公开(公告)号：US20140184296A1

公开(公告)日：2014-07-03

申请号：US13727850

申请日：2012-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsiung Lee ,  Shi-Hung Wang ,  Kuang-Kai Yen ,  Wei-Li Chen ,  Yung-Hsu Chuang ,  Shih-Hung Lan ,  Fan-Ming Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03K3/012 ,  H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/356043 ,  H03K3/3562

Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.

Abstract translation: 本公开涉及一种减少MCML逻辑器件的动态/静态功耗的装置和方法。 为了在断电模式下保持寄存器内容，公开了一种MCML保持锁存器和触发器。 保留MCML架构中的锁存电路用于在断电模式下保留关键寄存器内容，其中包括时钟树路径上的时钟缓冲器的组合逻辑被关闭以减少动态/静态功耗。 MCML保持触发器包括主锁存器和从锁存器，其中在断电模式期间将电源开关加到主锁存器以为主锁存器供电。 从锁存器包括保持有效的下拉电路，以使从锁存器在断电模式期间将数据保持在适当的电压电平。 还公开了其它装置和方法。

公开(公告)号：US09634096B2

公开(公告)日：2017-04-25

申请号：US14755990

申请日：2015-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/70 ,  H01L29/167 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

公开(公告)号：US09595589B2

公开(公告)日：2017-03-14

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L27/146 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。