公开(公告)号：US11853042B2

公开(公告)日：2023-12-26

申请号：US17177978

申请日：2021-02-17

申请人： Applied Materials, Inc.

发明人： Garrett Ho-Yee Sin ,  Sidharth Bhatia ,  Katty Marie Lydia Gamon Guyomard ,  Shawyon Jafari ,  Heng-Cheng Pai ,  Pramod Nambiar ,  Paul Lukas Brillhart ,  Ilker Durukan

IPC分类号： G05B19/418 ,  G06N20/00 ,  G01N33/00 ,  G06F30/398 ,  G06F119/22 ,  G06F119/18

CPC分类号： G05B19/41875 ,  G01N33/00 ,  G06F30/398 ,  G06N20/00 ,  G01N2033/0095 ,  G05B2219/31264 ,  G05B2219/32179 ,  G05B2219/45031 ,  G06F2119/18 ,  G06F2119/22

摘要： A method includes receiving part data associated with a corresponding part of substrate processing equipment, sensor data associated with one or more corresponding substrate processing operations performed by the substrate processing equipment to produce one or more corresponding substrates, and metrology data associated with the one or more corresponding substrates produced by the one or more corresponding substrate processing operations performed by the substrate processing equipment that includes the corresponding part. The method further includes generating sets of aggregated part-sensor-metrology data including a corresponding set of part data, a corresponding set of sensor data, and a corresponding set of metrology data. The method further includes causing analysis of the sets of aggregated part-sensor-metrology data to generate one or more outputs to perform a corrective action associated with the corresponding part of the substrate processing equipment.

公开(公告)号：US11768986B2

公开(公告)日：2023-09-26

申请号：US17438716

申请日：2020-03-13

申请人： XENERGIC AB

发明人： Tom Johansson ,  Hemanth Prabhu ,  Arturo Prieto Llorens ,  Babak Mohammadi

IPC分类号： G06F119/22 ,  G06F30/33

CPC分类号： G06F30/33 ,  G06F2119/22

摘要： A computer-implemented method for simulation of an integrated circuit for yield analysis includes: a) for plurality of variables, generating initial sampling sets by sampling from provided distributions related to physical properties of circuits; b) selecting at least one sample from each initial set randomly and combining into initial simulation set; c) running initial simulation of operation of circuit, applying initial simulation set, the operation having passing/failing criterion; d) if fails: storing samples of initial set into initial sampling distributions for each variable; e) repeating steps b)-d) until sufficient failures obtained; f) building importance sampling distribution based on each initial sampling distribution, the importance distribution having lower, center, upper portions; g) generating secondary simulation set by drawing samples from importance sampling distribution for each variable; h) simulating circuit by applying the secondary set; i) repeating steps g)-h); j) mapping resulting yields to provided distributions, to obtain a yield.

公开(公告)号：US11748529B2

公开(公告)日：2023-09-05

申请号：US17978960

申请日：2022-11-01

申请人： Turing Labs, Inc.

发明人： Manmit Shrimali ,  Ajith Govind ,  Michael L. Thompson

IPC分类号： G06F30/18 ,  H04L67/12 ,  G06F119/22 ,  G06F111/00 ,  G06F30/12

CPC分类号： G06F30/18 ,  G06F30/12 ,  G06F2111/00 ,  G06F2119/22 ,  H04L67/12

摘要： A method and system for an accelerated design of a virtual product formulation based on an expert-enhanced quantitative formulation network includes sourcing qualitative expert formulation; creating a qualitative formulation network; extracting qualitative network-expansion data based on a category associated with a target product associated with the qualitative formulation network, creating a second set of network components including formulation variable nodes and formulation edge connections; integrating the second set of network components into the qualitative formulation network; transforming the qualitative formulation network integrated with the second set of network components to a quantitative formulation network; designing at least part of a virtual product formulation based on the quantitative formulation network; and generating a target formulation proposal that likely satisfies the target formulation objective based on executing the virtual product formulation as initialized.

公开(公告)号：US11630931B2

公开(公告)日：2023-04-18

申请号：US16948126

申请日：2020-09-03

申请人： Virtual Vehicle Research GmbH

发明人： Stefan Harald Reiterer ,  Martin Benedikt

IPC分类号： G06F30/23 ,  G06T17/20 ,  G06F30/367 ,  G06F119/22 ,  G06F30/25 ,  G06F111/00 ,  G06F30/398

摘要： A computer-implemented method of generating an operation procedure for a simulation of a system, in particular a mechatronic system is disclosed. A source node has at least one source parameter (Ps) and a first simulation system with at least one first simulation node is determined, wherein the first simulation node includes at least one input parameter (Pi) and at least one output parameter (Pa). The first simulation node includes a simulation function for determining the output parameter (Pa) based on the input parameter (Pi) of the first node. When the input parameter (Pi) is available based on the source parameter (Ps), a global operation graph is built describing a link between the source node and the first simulation node for describing an operating procedure of the simulation of the system.

公开(公告)号：US11593538B2

公开(公告)日：2023-02-28

申请号：US16373192

申请日：2019-04-02

申请人： Accenture Global Solutions Limited

发明人： Emanuele Procaccioli ,  Ettore Moroni ,  Fabio Lattanzio ,  Diego Berti

IPC分类号： G06F30/18 ,  G06F16/787 ,  H04L9/32 ,  G06F30/12 ,  G06F111/00 ,  G06F119/22

摘要： A device receives an infrastructure design document that represents a network infrastructure design. The device causes the infrastructure design document to be displayed via a first interface of a geographic information system (GIS) tool that is to be used during an inspection of a site, where the inspection includes inspecting structural components that are to support equipment of a network. The device receives, from a user device, feedback data that is based on the inspection. The device causes the feedback data to be integrated into the GIS tool. The device receives, from another user device, instructions that are to be used to update the infrastructure design document. The device updates the infrastructure design document based on the set of instructions and performs actions that allow the infrastructure design document to be used when implementing the network infrastructure design.

公开(公告)号：US11314918B1

公开(公告)日：2022-04-26

申请号：US17080161

申请日：2020-10-26

申请人： SAMSUNG SDS CO., LTD.

发明人： Rak Kyeong Seong ,  Jae Ho Yang ,  Sang Hoon Han ,  Joung Oh Yun

IPC分类号： G06F30/347 ,  G06F119/22 ,  G06F30/394 ,  G06F111/10 ,  G06F113/18 ,  G06F115/10

摘要： A method for path routing according to an embodiment of the present disclosure may include selecting a first start point and a first end point with which path routing is performed in a circular frame generated by connecting all points included in one or more start point sets included in a layer, one or more end point sets paired with the start point set, and one or more edge point pair sets to one closed curve, generating a connectivity graph by connecting edge points included in one or more nodes corresponding to segments obtained by dividing the circular frame into one or more regions, and connecting the first start point and the first end point based on a cost for connecting the first start point and the first end point calculated using the connectivity graph.

公开(公告)号：US11062072B1

公开(公告)日：2021-07-13

申请号：US16912006

申请日：2020-06-25

申请人： University of Electronic Science and Technology of China

发明人： Yuehang Xu ,  Shuman Mao ,  Yunqiu Wu

IPC分类号： G06F30/30 ,  G06F30/367 ,  G06F30/373 ,  G06F119/22 ,  G06F119/06

摘要： A yield load pull system-based integrated circuit design method and a system thereof are provided. The method includes: setting a yield-related threshold; setting a source impedance; configuring a sweep range of a Smith chart; determining load impedance points within the sweep range of the Smith chart; acquiring impedance information; determining output characteristics of a plurality of sample devices at each load impedance point of the determined load impedance points, based on the source impedance and the impedance information corresponding to each load impedance point, by invoking a harmonic balance simulator embedded in an Advanced Design System, where the output characteristics comprise: a large-signal gain, an output power and a power-added efficiency; determining a device yield for each load impedance point; for each output characteristic calculating a mean value across the plurality of sample devices, at each load impedance point; and determining a best load impedance; conducting IC design.

公开(公告)号：US10690722B1

公开(公告)日：2020-06-23

申请号：US16271265

申请日：2019-02-08

申请人： Pranav Ashar

发明人： Pranav Ashar ,  Fabrice Baray ,  Hari Mony ,  Nikhil Rahagude ,  Vikas Sachdeva

IPC分类号： G06F30/30 ,  G01R31/317 ,  G01R31/3177 ,  G06F30/33 ,  G06F30/3315 ,  G06F111/00 ,  G06F30/3308 ,  G06F30/3312 ,  G06F119/22

摘要： Methods and systems are described to efficiently identify the potential for failures in integrated circuits (ICs) caused by glitches. In an IC based on synchronous operation, the operation of the multiplicity of inputs, storage elements and observed outputs in said IC are synchronized to one or more clocks that determine the specific times at which inputs change, outputs are observed, and stored values are updated. Almost all ICs are based on synchronous operation. When input values to a logic circuit in an IC change, the effects of said changes propagate through paths in said logic circuit in a delayed manner such that each of said paths may have a different delay. Said different delays can cause a wire in a logic circuit to have transient values (termed “glitch”) before settling to a final value consistent with the input values being applied to said logic circuit. An IC is likely to function erroneously, referred to as having a “glitch failure”, when a glitch value is observed at an output or captured by a storage element. Glitch failures are difficult and expensive to diagnose in a manufactured IC. To raise the productivity of IC development, it is imperative that any potential glitch failure in an IC be detected prior to manufacture. Said detection is hard because a typical IC has a very large number of logic circuits to analyze for glitch failure. To be practical, said analysis must have high performance and high accuracy. Said high performance requiring that said analysis should complete in acceptable run time even for the largest ICs. Said high accuracy requires that said analysis should identify all potential for glitch failure (100% recall), and minimize the number of logic circuits erroneously reported as having glitch failure potential (high precision). Whereas the glitch phenomenon, the potential for glitch failure and methods for detecting glitch failures in pre-manufacture IC models are well known, achievement of high performance with high accuracy has not yet been addressed in prior art. Whereas conventional methods for glitch checking are inefficient and insufficiently accurate, the methods and systems described in the present invention achieve new levels of performance, scalability and accuracy in said detection of glitch failures in an IC. Said methods and systems are based on a novel dissection of glitch-checking requirements into a multiplicity of individual steps, which said steps executed in a systematic sequence deliver high performance and accuracy.

公开(公告)号：US12112108B2

公开(公告)日：2024-10-08

申请号：US17433595

申请日：2020-02-26

申请人： Synopsys, Inc.

发明人： Jiayong Le ,  Wenwen Chai ,  Li Ding

IPC分类号： G06F30/3312 ,  G06F30/337 ,  G06F111/08 ,  G06F119/22

CPC分类号： G06F30/3312 ,  G06F30/337 ,  G06F2111/08 ,  G06F2119/22

摘要： Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.

公开(公告)号：US12055904B2

公开(公告)日：2024-08-06

申请号：US17293373

申请日：2019-10-30

申请人： ASML NETHERLANDS B.V.

发明人： Youping Zhang ,  Boris Menchtchikov ,  Cyrus Emil Tabery ,  Yi Zou ,  Chenxi Lin ,  Yana Cheng ,  Simon Philip Spencer Hastings ,  Maxime Philippe Frederic Genin

IPC分类号： G06F30/10 ,  G03F7/00 ,  G05B13/02 ,  G05B13/04 ,  G06F30/27 ,  G06N3/045 ,  G06N3/08 ,  G06F119/02 ,  G06F119/22

CPC分类号： G05B13/048 ,  G03F7/705 ,  G03F7/70616 ,  G03F7/706837 ,  G05B13/027 ,  G05B13/042 ,  G06F30/10 ,  G06F30/27 ,  G06N3/045 ,  G06N3/08 ,  G06F2119/02 ,  G06F2119/22

摘要： A method for predicting yield relating to a process of manufacturing semiconductor devices on a substrate, the method including: obtaining a trained first model which translates modeled parameters into a yield parameter, the modeled parameters including: a) a geometrical parameter associated with one or more selected from: a geometric characteristic, dimension or position of a device element manufactured by the process and b) a trained free parameter; obtaining process parameter data including data regarding a process parameter characterizing the process; converting the process parameter data into values of the geometrical parameter; and predicting the yield parameter using the trained first model and the values of the geometrical parameter.