公开(公告)号：US20230009820A1

公开(公告)日：2023-01-12

申请号：US17591416

申请日：2022-02-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Ting YEN ,  Wei-Ting YEH ,  Shih-Cheng CHEN ,  Yu-Yun PENG

IPC: H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

公开(公告)号：US20250014943A1

公开(公告)日：2025-01-09

申请号：US18219259

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng Yong LIANG ,  Wei-Ting YEH ,  I-Han HUANG ,  Chen-Hao WU ,  An-Hsuan LEE ,  Huang-Lin CHAO ,  Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/3105 ,  H01L23/00 ,  H01L29/66

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

公开(公告)号：US20220415696A1

公开(公告)日：2022-12-29

申请号：US17702238

申请日：2022-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting YEH ,  Zheng Yong Liang ,  De-Yang Chiou ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/683 ,  H01L21/762

Abstract: The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.