公开(公告)号：US11942358B2

公开(公告)日：2024-03-26

申请号：US17200223

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Ko-Feng Chen ,  Zheng-Yong Liang ,  Chen-Han Wang ,  De-Yang Chiou ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/76224 ,  H01L21/31116 ,  H01L21/823481

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures.

公开(公告)号：US20220415696A1

公开(公告)日：2022-12-29

申请号：US17702238

申请日：2022-03-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting YEH ,  Zheng Yong Liang ,  De-Yang Chiou ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/683 ,  H01L21/762

Abstract: The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

公开(公告)号：US20220293458A1

公开(公告)日：2022-09-15

申请号：US17200223

申请日：2021-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Ko-Feng Chen ,  Zheng Yong Liang ,  Chen-Han Wang ,  De-Yang Chiou ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8234

Abstract: The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures

公开(公告)号：US11362038B2

公开(公告)日：2022-06-14

申请号：US17062677

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  G03F1/42 ,  G03F1/70 ,  H01L21/66

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.

公开(公告)号：US20210375781A1

公开(公告)日：2021-12-02

申请号：US17062677

申请日：2020-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yeong-Jyh Lin ,  Ching I Li ,  De-Yang Chiou ,  Sz-Fan Chen ,  Han-Jui Hu ,  Ching-Hung Wang ,  Ru-Liang Lee ,  Chung-Yi Yu

IPC: H01L23/544 ,  H01L21/027 ,  H01L21/683 ,  H01L21/66 ,  G03F1/42 ,  G03F1/70

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a plurality of upper alignment marks on a semiconductor wafer. A plurality of lower alignment marks is formed on a handle wafer and correspond to the upper alignment marks. The semiconductor wafer is bonded to the handle wafer such that centers of the upper alignment marks are laterally offset from centers of corresponding lower alignment marks. An overlay (OVL) shift is measured between the handle wafer and the semiconductor wafer by detecting the plurality of upper alignment marks and the plurality of lower alignment marks. A photolithography process is performed by a photolithography tool to partially form an integrated circuit (IC) structure over the semiconductor wafer. During the photolithography process the photolithography tool is compensatively aligned according to the OVL shift.