公开(公告)号：US20190103283A1

公开(公告)日：2019-04-04

申请号：US16053981

申请日：2018-08-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Hao WU ,  Shen-Nan LEE ,  Chung-Wei HSU ,  Tsung-Ling TSAI ,  Teng-Chun TSAI

IPC: H01L21/321 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

Abstract: A method for manufacturing a semiconductor device includes forming a gate electrode over a substrate; forming a hard mask over the gate electrode, in which the hard mask comprises a metal oxide; forming an interlayer dielectric (ILD) layer over the hard mask; forming a contact hole in the ILD layer, wherein the contact hole exposes a source/drain; filling the contact hole with a conductive material; and applying a chemical mechanical polish process to the ILD layer and the conductive material, wherein the chemical mechanical polish process stops at the hard mask, the chemical mechanical polish process uses a slurry containing a boric acid or its derivative, the chemical mechanical polish process has a first removal rate of the ILD layer and a second removal rate of the hard mask, and a first ratio of the first removal rate to the second removal rate is greater than about 5.

公开(公告)号：US20200091007A1

公开(公告)日：2020-03-19

申请号：US16277326

申请日：2019-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chu-An LEE ,  Chen-Hao WU ,  Peng-Chung JANGJIAN ,  Chun-Wen HSIAO ,  Teng-Chun TSAI ,  Huang-Lin CHAO

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.

公开(公告)号：US20210098283A1

公开(公告)日：2021-04-01

申请号：US16953949

申请日：2020-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Teng-Chun TSAI ,  Chen-Hao WU ,  Chu-An LEE ,  Chun-Hung LIAO ,  Tsung-Ling TSAI

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor structure is provided, including a conductive layer, a dielectric layer over the conductive layer, a ruthenium material in the dielectric layer and in contact with a portion of the conductive layer, and a ruthenium oxide material in the dielectric layer laterally between the ruthenium material and the dielectric layer.

公开(公告)号：US20250014943A1

公开(公告)日：2025-01-09

申请号：US18219259

申请日：2023-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng Yong LIANG ,  Wei-Ting YEH ,  I-Han HUANG ,  Chen-Hao WU ,  An-Hsuan LEE ,  Huang-Lin CHAO ,  Yu-Yun PENG ,  Keng-Chu LIN

IPC: H01L21/768 ,  H01L21/3105 ,  H01L23/00 ,  H01L29/66

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

公开(公告)号：US20220362906A1

公开(公告)日：2022-11-17

申请号：US17866538

申请日：2022-07-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Te-Chien HOU ,  Teng-Chun TSAI ,  Chung-Wei HSU ,  Chen-Hao WU

IPC: B24B53/017 ,  B24B49/12 ,  B24B37/32 ,  B24B49/00

Abstract: A method includes measuring a first thickness at a first location of the polishing pad and a second thickness at a second location of the polishing pad; obtaining a first reference thickness at the first location of the polishing pad, wherein the first reference thickness is an average thickness of multiple thicknesses at the first location; obtaining a second reference thickness at the second location of the polishing pad, wherein the second reference thickness is an average thickness of multiple thicknesses at the second location; calculating a first thickness difference; calculating a second thickness difference; modifying a conditioning parameter value at the first location of the polishing pad; and sweeping a conditioner across a surface of the polishing pad; and applying a downforce or a sweeping speed to the conditioner that urges the conditioner against the first location of the polishing pad according to the modified conditioning parameter value.

公开(公告)号：US20200090983A1

公开(公告)日：2020-03-19

申请号：US16129899

申请日：2018-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Teng-Chun TSAI ,  Chen-Hao WU ,  Chu-An LEE ,  Chun-Hung LIAO ,  Tsung-Ling TSAI

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method of manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer; removing a portion of the dielectric layer to form an opening exposing a portion of the conductive layer; filling a ruthenium-containing material in the opening and in contact with the dielectric layer; and polishing the ruthenium-containing material using a slurry including an abrasive and an oxidizer selected from the group consisting of hydrogen peroxide (H2O2), potassium periodate (KIO4), potassium iodate (KIO3), potassium permanganate (KMnO4), iron(III) nitrate (FeNO3) and a combination thereof.

公开(公告)号：US20190160628A1

公开(公告)日：2019-05-30

申请号：US16141680

申请日：2018-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shen-Nan LEE ,  Te-Chien HOU ,  Teng-Chun TSAI ,  Chung-Wei HSU ,  Chen-Hao WU

IPC: B24B53/017

Abstract: A method is provided and includes: measuring a surface profile of a polishing pad; obtaining a reference profile of the polishing pad; comparing the surface profile of the polishing pad with the reference profile to generate a difference result; determining a conditioning parameter value according to the difference result; and conditioning the polishing pad using the conditioning parameter value.

公开(公告)号：US20190096686A1

公开(公告)日：2019-03-28

申请号：US16138632

申请日：2018-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Wei HSU ,  Yu-Chung SU ,  Chen-Hao WU ,  Shen-Nan LEE ,  Tsung-Ling TSAI ,  Teng-Chun TSAI

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/306

Abstract: A method includes forming a spin-on carbon (SOC) layer over a target structure; chemically treating an upper portion of the SOC layer; forming a sacrificial layer over the SOC layer; performing a chemical mechanical polish (CMP) process on the sacrificial layer until reaching the SOC layer, wherein the chemically treated upper portion of the SOC layer has a higher resistance to the CMP process than that of the sacrificial layer; forming a patterned photoresist layer over the SOC layer after the CMP process; and etching the target structure using the patterned photoresist layer as a mask.