公开(公告)号：US20170053844A1

公开(公告)日：2017-02-23

申请号：US14830740

申请日：2015-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ching Tsai ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L21/66 ,  H01L23/31 ,  H01L21/82 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/538 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/08235 ,  H01L2924/37001

Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.

Abstract translation: 提供了一种三维集成电路结构，其包括第一裸片，直通衬底通孔和连接器。 第一裸片与第一裸片的第一电介质层和第二裸片的第二电介质层结合到第二裸片，其中第一钝化层位于第一电介质层与第一裸片的第一衬底之间， 第一测试垫被嵌入在第一钝化层中。 穿通基板通孔穿过第一管芯并与第二管芯电连接。 连接器通过贯通基板通孔电连接到第一管芯和第二管芯。

公开(公告)号：US09633917B2

公开(公告)日：2017-04-25

申请号：US14830740

申请日：2015-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ching Tsai ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/82

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L23/3171 ,  H01L23/538 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/09 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/08235 ,  H01L2924/37001

Abstract: Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.