公开(公告)号：US20180090460A1

公开(公告)日：2018-03-29

申请号：US15666309

申请日：2017-08-01

Applicant: Microchip Technology Incorporated

Inventor： George Chu

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  C23C14/34 ,  C25D5/02

CPC classification number: H01L24/13 ,  C23C14/34 ,  C25D5/022 ,  H01L21/76885 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02311 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/07025

Abstract: A copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding and in the vicinity of the copper pillar bumps only. The organic insulation layer, typically a thin film polymer layer, acts as a barrier layer for the copper pillar bumps to protect the semiconductor wafer during the copper pillar flip chip bonding process. The copper pillar bump semiconductor packaging method limits the areas where the organic insulation layer is applied to reduce the stress introduced to the semiconductor wafer by the organic insulation layer. In another embodiment, a copper pillar bump semiconductor packaging method patterns an organic insulation layer formed under the copper pillar bumps to areas surrounding the copper pillar bumps and along the path of a redistribution layer without using a large and continuous organic insulation layer.

公开(公告)号：US20170278809A1

公开(公告)日：2017-09-28

申请号：US15342838

申请日：2016-11-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： WEI-LI HUANG ,  JHENG-JIE WONG ,  HSIANG-SHENG SU ,  TSUNG-LUNG HUANG ,  KUO-CHIO LIU ,  HSIN-CHIEH HUANG ,  DE-DUI MARVIN LIAO ,  CHIN-YU KU ,  CHEN-SHIEN CHEN

IPC: H01L23/00 ,  H01L21/02

CPC classification number: H01L24/02 ,  H01L21/02334 ,  H01L21/0234 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/42 ,  H01L2224/02235 ,  H01L2224/02251 ,  H01L2224/02255 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0381 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/131 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/35121 ,  H01L2924/00014

Abstract: A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer.

公开(公告)号：US09640496B2

公开(公告)日：2017-05-02

申请号：US14857549

申请日：2015-09-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Wei-Yu Chen ,  Hsien-Wei Chen ,  An-Jhih Su ,  Cheng-Hsien Hsieh

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/024

Abstract: A semiconductor device includes a semiconductor substrate, and a redistribution layer (RDL) over the semiconductor substrate and configured to receive a bump. The semiconductor device further includes a polymeric material over the RDL, and the polymeric material includes an opening to expose a portion of the RDL. In the semiconductor device, a barrier is covering a joint between the polymeric material and the RDL.

公开(公告)号：US09607958B2

公开(公告)日：2017-03-28

申请号：US14512614

申请日：2014-10-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13008 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/20101 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

公开(公告)号：US20170062361A1

公开(公告)日：2017-03-02

申请号：US15186903

申请日：2016-06-20

Applicant: Renesas Electronics Corporation

Inventor： Akira YAJIMA

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/02315 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02373 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/364 ,  H01L2924/365 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01007 ,  H01L2924/01074 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00013

Abstract: Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

Abstract translation: 提高了半导体器件的可靠性。 在再分配层的互连宽度方向的剖视图中，在互连沟槽的侧面上设置斜面。 互连宽度方向上的互连沟槽的最大开口宽度大于互连宽度方向上的再分配层的最大互连宽度，并且设置互连沟槽以在平面图中封装再分配层。

公开(公告)号：US09281234B2

公开(公告)日：2016-03-08

申请号：US13892685

申请日：2013-05-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L21/76802 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Disclosed herein is an interconnect apparatus comprising a substrate having a land disposed thereon and a passivation layer disposed over the substrate and over a portion of the land. An insulation layer is disposed over the substrate and has an opening disposed over at least a portion of the land. A conductive layer is disposed over a portion of the passivation layer and in electrical contact with the land. The conductive layer has a portion extending over at least a portion of the insulation layer. The conductive layer comprises a contact portion disposed over at least a portion of the land. The insulation layer avoids extending between the land and the contact portion. A protective layer may be disposed over at least a portion of the conductive layer and may optionally have a thickness of at least 7 μm.

Abstract translation: 本文公开了一种互连装置，其包括具有设置在其上的焊盘的衬底和设置在衬底上并在焊盘的一部分上方的钝化层。 绝缘层设置在衬底上并且具有设置在焊盘的至少一部分上的开口。 导电层设置在钝化层的一部分上并与焊盘电接触。 导电层具有在绝缘层的至少一部分上延伸的部分。 导电层包括设置在焊盘的至少一部分上的接触部分。 绝缘层避免了在焊盘和接触部分之间的延伸。 保护层可以设置在导电层的至少一部分上，并且可以任选地具有至少7μm的厚度。

公开(公告)号：US20150279796A1

公开(公告)日：2015-10-01

申请号：US14306905

申请日：2014-06-17

Applicant: Lingsen Precision Industries Ltd.

Inventor： Ming-Te TU ,  Ching-I LIN ,  Chia-Jen HSU ,  Sheng-Jen LIN

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L21/78 ,  H01L21/304

CPC classification number: H01L24/14 ,  H01L21/304 ,  H01L21/561 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/4985 ,  H01L23/528 ,  H01L24/02 ,  H01L24/11 ,  H01L24/13 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02321 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/12042 ,  H01L2924/401 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2924/00012

Abstract: A method of manufacturing a quad-flat no-leads package (QFN) structure includes: forming a conducting layer on a surface of a thin-film layer; forming a plurality of conduction wirings from the conducting layer by a means of circuit layout; electrically connecting contact pads of a die to front ends of the conduction wirings, respectively; forming a plurality of through-holes in the thin-film layer by a means of drilling, such that terminal ends of the conduction wirings are exposed from the through-holes, respectively; and forming a plurality of metal bumps at the through-holes, respectively, such that signals from the die are sent to a bottom surface of the thin-film layer through the conduction wirings. Hence, the QFN structure and the method of manufacturing the same based on application of wafer-level chip-scale package (WLCSP) and extension of tape QFN to simplify the package manufacturing process, cut production costs, and enhance production yield.

Abstract translation: 制造四平面无引线封装（QFN）结构的方法包括：在薄膜层的表面上形成导电层; 通过电路布局从导电层形成多个导电布线; 分别将管芯的接触垫电连接到导电布线的前端; 通过钻孔在薄膜层中形成多个通孔，使得导电布线的末端分别从通孔露出; 并且在通孔处分别形成多个金属凸块，使得来自模具的信号通过导电布线被送到薄膜层的底表面。 因此，基于晶片级芯片级封装（WLCSP）的应用和带式QFN的扩展，QFN结构及其制造方法简化了封装制造工艺，降低了生产成本，提高了生产成本。

公开(公告)号：US20140151885A1

公开(公告)日：2014-06-05

申请号：US14012211

申请日：2013-08-28

Applicant: Timo Benzel

Inventor： Peter SCHMOLLNGRUBER ,  Hubert BENZEL ,  Hans ARTMANN ,  Viktor MOROSOW

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53266 ,  G01L19/0069 ,  G01L19/0627 ,  H01L21/7685 ,  H01L23/291 ,  H01L23/3178 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53252 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05093 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05669 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate which has at least one doped contact area and at least one line which is formed on the substrate and which is electrically connected to the at least one contact area, and at least one diffusion barrier, which includes at least one metal applied on a contact surface of the associated contact area, being formed between the at least one line and the at least one associated contact area, the at least one metal forming multiple metal-plated subareas which contact the contact surface of the same contact area and which are separated from one another. Furthermore, a manufacturing method for a semiconductor device is described.

Abstract translation: 半导体器件包括具有至少一个掺杂接触面积的衬底和形成在衬底上并且至少一个电连接至该至少一个接触区域的至少一条线，以及至少一个扩散阻挡层，其包括至少一个 施加在所述相关接触区域的接触表面上的金属，形成在所述至少一个线与所述至少一个相关联的接触区域之间，所述至少一个金属形成多个金属镀层子区域，所述子区域与所述相同接触区域的接触表面接触 并且彼此分离。 另外，对半导体装置的制造方法进行说明。

公开(公告)号：US20140117535A1

公开(公告)日：2014-05-01

申请号：US13664812

申请日：2012-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05575 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/06102 ,  H01L2224/11848 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

Abstract translation: 制造倒装芯片封装的结构和方法，其采用距离用于倒装芯片封装的集成电路（IC）芯片的中心的径向距离的不同高度的聚酰亚胺焊盘。 聚酰亚胺焊盘可以形成在电连接器下面，电连接器将IC芯片连接到倒装芯片封装的芯片载体，使得形成在更高高度的聚酰亚胺焊盘上的电连接器设置在离IC芯片中心更大的径向距离处 而形成在较低高度的聚酰亚胺焊盘上的电连接器更靠近IC芯片的中心设置。 与IC芯片表面相对高的电连接器可以补偿在制造倒装芯片封装期间由热引起的翘曲产生的间隙，其将IC芯片上的电连接器与芯片载体上的倒装芯片分离 。

公开(公告)号：US20130328192A1

公开(公告)日：2013-12-12

申请号：US13739547

申请日：2013-01-11

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Jeong Seok Lee ,  In Tae Kim ,  Jae Sik Park ,  Dai Hyun Jung

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0231 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05555 ,  H01L2224/056 ,  H01L2224/06133 ,  H01L2224/06135 ,  H01L2224/10126 ,  H01L2224/13006 ,  H01L2224/13008 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2924/014 ,  H01L2924/00014

Abstract: One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.

Abstract translation: 一个实施例通过使用镀有种子层的光致抗蚀剂图案形成从半导体芯片的焊盘延伸的再分配层来提供半导体封装。 半导体封装的制造相对简单，从而缩短制造时间并降低制造成本，并且可以增加输入/输出端子的粘附面积，并且可以防止将输入/输出端子连接和焊接到一对再分布层上的分层 。