公开(公告)号：US12279437B2

公开(公告)日：2025-04-15

申请号：US18362817

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

公开(公告)号：US11800724B2

公开(公告)日：2023-10-24

申请号：US17562949

申请日：2021-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

公开(公告)号：US11244983B2

公开(公告)日：2022-02-08

申请号：US16893010

申请日：2020-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You ,  Hung Cho Wang ,  Yen-Yu Shih

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: The present disclosure provides a system and method for forming a reduced area MRAM memory cell including a substrate, a transistor overlying the substrate and a magnetic tunnel junction overlying the transistor. The transistor includes a first and second source regions, a drain region between the first and second source regions, at least one first channel region between the drain region and the first source region, at least one second channel region between the drain region and the second source region, a first gate structure overlying the at least one first channel region, and a second gate structure overlying the at least one second channel region. First and second metal layers overlie the transistor. The first and second metal layers are configured to couple a common source line signal to the first and second source regions.