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公开(公告)号：US20190123271A1
公开(公告)日：2019-04-25
申请号：US16227096
申请日：2018-12-20
发明人： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
摘要： The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.
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公开(公告)号：US10199575B2
公开(公告)日：2019-02-05
申请号：US15223399
申请日：2016-07-29
发明人： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
摘要： The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode. The top electrode via has a smaller total width than the top electrode.
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公开(公告)号：US10134807B2
公开(公告)日：2018-11-20
申请号：US15460902
申请日：2017-03-16
摘要： Integrated circuit structures and methods for forming the same are provided. An integrated circuit includes a dielectric layer in a memory region and a logic region. The integrated circuit structure also includes a first conductive feature in the dielectric layer in the memory region. The integrated circuit structure further includes a second conductive feature in the dielectric layer in the logic region. In addition, the integrated circuit structure includes an active memory cell over the dielectric layer in the memory region. The active memory cell is connected to the first conductive feature. The integrated circuit structure also includes a dummy memory cell over the dielectric layer in the logic region. The dummy memory cell is connected to the second conductive feature.
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公开(公告)号：US10043970B2
公开(公告)日：2018-08-07
申请号：US15449284
申请日：2017-03-03
摘要： The present disclosure relates to a method for determining a characteristic of a monitored layer of an integrated chip structure. In some embodiments, the method may be performed by forming an integrated chip structure over a substrate. The method further includes forming a monitor layer over the integrated chip structure. The monitor layer includes a plurality of monitor pads. The method also includes measuring an electrical property between a set of monitor pads of the plurality of monitor pads. The set of monitor pads are laterally spaced apart by a monitor pad distance. A characteristic of a region of the integrated chip structure underlying the monitor pad distance between the set of monitor pads is determined based on the measured electrical property.
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公开(公告)号：US20180175288A1
公开(公告)日：2018-06-21
申请号：US15449284
申请日：2017-03-03
CPC分类号： H01L43/12 , H01L22/12 , H01L22/32 , H01L27/222 , H01L43/02
摘要： The present disclosure relates to a method for determining a characteristic of a monitored layer of an integrated chip structure. In some embodiments, the method may be performed by forming an integrated chip structure over a substrate. The method further includes forming a monitor layer over the integrated chip structure. The monitor layer includes a plurality of monitor pads. The method also includes measuring an electrical property between a set of monitor pads of the plurality of monitor pads. The set of monitor pads are laterally spaced apart by a monitor pad distance. A characteristic of a region of the integrated chip structure underlying the monitor pad distance between the set of monitor pads is determined based on the measured electrical property.
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公开(公告)号：US20180019390A1
公开(公告)日：2018-01-18
申请号：US15715413
申请日：2017-09-26
发明人： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC分类号： H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
摘要： Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.
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7.发明申请公开(公告)号：US20170256704A1
公开(公告)日：2017-09-07
申请号：US15601095
申请日：2017-05-22
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.
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公开(公告)号：US11653572B2
公开(公告)日：2023-05-16
申请号：US17184997
申请日：2021-02-25
CPC分类号： H01L43/12 , H01L27/228 , H01L43/08
摘要： Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.
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公开(公告)号：US11075335B2
公开(公告)日：2021-07-27
申请号：US16408815
申请日：2019-05-10
发明人： Harry-Hak-Lay Chuang , Chen-Pin Hsu , Hung Cho Wang , Wen-Chun You , Sheng-Chang Chen , Tsun Chung Tu , Jiunyu Tsai , Sheng-Huang Huang
IPC分类号： H01L21/768 , H01L43/12 , H01L43/02 , H01F10/32 , H01L27/22 , H01L23/528 , H01F41/32 , H01L23/522
摘要： Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.
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公开(公告)号：US20210184110A1
公开(公告)日：2021-06-17
申请号：US17184997
申请日：2021-02-25
摘要： Some embodiments relate to a magnetoresistive random-access memory (MRAM) cell. The cell includes a bottom electrode having a central bottom electrode portion surrounded by a peripheral bottom electrode portion. Step regions of the conductive bottom electrode couple the central and peripheral bottom electrode portions to one another such that an upper surface of the central portion is recessed relative to an upper surface of the peripheral portion. A magnetic tunneling junction (MTJ) has MTJ outer sidewalls which are disposed over the bottom central electrode portion and which are arranged between the step regions. A top electrode is disposed over an upper surface of the MTJ. Other devices and methods are also disclosed.
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