公开(公告)号：US10468500B1

公开(公告)日：2019-11-05

申请号：US16024506

申请日：2018-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223 ,  H01L21/8234

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US12068392B2

公开(公告)日：2024-08-20

申请号：US17654807

申请日：2022-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/223 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234

CPC classification number: H01L29/665 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66515 ,  H01L29/66795

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.

公开(公告)号：US11276766B2

公开(公告)日：2022-03-15

申请号：US16673661

申请日：2019-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Cheng-Yi Peng ,  Yin-Pin Wang ,  Kuo-Feng Yu ,  Da-Wen Lin ,  Jian-Hao Chen ,  Shahaji B. More

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768 ,  H01L21/223

Abstract: A method and structure for doping source and drain (S/D) regions of a PMOS and/or NMOS FinFET device are provided. In some embodiments, a method includes providing a substrate including a fin extending therefrom. In some examples, the fin includes a channel region, source/drain regions disposed adjacent to and on either side of the channel region, a gate structure disposed over the channel region, and a main spacer disposed on sidewalls of the gate structure. In some embodiments, contact openings are formed to provide access to the source/drain regions, where the forming the contact openings may etch a portion of the main spacer. After forming the contact openings, a spacer deposition and etch process may be performed. In some cases, after performing the spacer deposition and etch process, a silicide layer is formed over, and in contact with, the source/drain regions.