公开(公告)号：US10141934B2

公开(公告)日：2018-11-27

申请号：US15794331

申请日：2017-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tao Yang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: H03K19/017 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H03K19/0185

Abstract: A level shifter circuit includes a latch module with a first plurality of PMOS transistors and a second plurality of NMOS transistors; a MOS module with a third plurality of MOS transistors operatively connected to the latch module; a fourth plurality of transistors operatively connected between the MOS module and the ground; and a fifth plurality of capacitors operatively connected between the latch module and the gates of fourth plurality of transistors.

公开(公告)号：US10281501B2

公开(公告)日：2019-05-07

申请号：US15628393

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Tao Yang ,  Wen-Shen Chou ,  Yung-Chow Peng

IPC: G01R19/04 ,  G01R31/26 ,  H03L7/18 ,  H03J3/12 ,  H04L27/20 ,  G01R31/28

Abstract: A peak current evaluation apparatus for an IC is provided. The peak current evaluation apparatus includes a pulse tuner and a testing circuit. The pulse tuner receives a clock signal, adjusts pulse width and duty ratio of the clock signal according to at least one predetermined parameter in order to generate a pulse signal with a stress voltage. The testing circuit is coupled to the pulse tuner. The testing circuit, which includes two input ports, receives the pulse signal at one of the two input ports in order to stress a testing device, measures the resistance value of the testing device, and calculates the peak current of the testing device when the resistance value increases and exceeds a threshold value.