公开(公告)号：US11652054B2

公开(公告)日：2023-05-16

申请号：US17236234

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76895

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US20220344264A1

公开(公告)日：2022-10-27

申请号：US17236234

申请日：2021-04-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/535 ,  H01L21/768

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.

公开(公告)号：US11482447B2

公开(公告)日：2022-10-25

申请号：US16923424

申请日：2020-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

摘要： The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11362030B2

公开(公告)日：2022-06-14

申请号：US16887475

申请日：2020-05-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Teng Dai ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Hsi-Wen Tien ,  Wei-Hao Liao

IPC分类号： H01L21/00 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

摘要： Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.

公开(公告)号：US20210391261A1

公开(公告)日：2021-12-16

申请号：US16898705

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

摘要： The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

公开(公告)号：US11302641B2

公开(公告)日：2022-04-12

申请号：US16898705

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Hao Liao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768

摘要： The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.

公开(公告)号：US20220013403A1

公开(公告)日：2022-01-13

申请号：US16923424

申请日：2020-07-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/532

摘要： The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

公开(公告)号：US11488926B2

公开(公告)日：2022-11-01

申请号：US16898670

申请日：2020-06-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L23/00 ,  H01L21/768

摘要： The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.

公开(公告)号：US20210193513A1

公开(公告)日：2021-06-24

申请号：US17012427

申请日：2020-09-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/522

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.

公开(公告)号：US11521896B2

公开(公告)日：2022-12-06

申请号：US17012427

申请日：2020-09-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsi-Wen Tien ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsin-Chieh Yao ,  Yu-Teng Dai ,  Wei-Hao Liao

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L27/092

摘要： In some embodiments, the present disclosure relates to an integrated chip that includes a lower conductive structure arranged over a substrate. An etch stop layer is arranged over the lower conductive structure, and a first interconnect dielectric layer is arranged over the etch stop layer. The integrated chip further includes an interconnect via that extends through the first interconnect dielectric layer and the etch stop layer to directly contact the lower conductive structure. A protective layer surrounds outermost sidewalls of the interconnect via.