公开(公告)号：US12165947B2

公开(公告)日：2024-12-10

申请号：US17217868

申请日：2021-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Sheh Huang ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

公开(公告)号：US11923295B2

公开(公告)日：2024-03-05

申请号：US16906659

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Wei Chan ,  Yung-Shih Cheng ,  Wen-Sheh Huang ,  Yu-Hsiang Chen

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5228 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226

Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.

公开(公告)号：US20220310556A1

公开(公告)日：2022-09-29

申请号：US17350856

申请日：2021-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng

IPC: H01L23/00 ,  H01L23/528

Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.

公开(公告)号：US11437313B2

公开(公告)日：2022-09-06

申请号：US17111417

申请日：2020-12-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Wei Chan ,  Yung-Shih Cheng ,  Wen-Sheh Huang

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L49/02

Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.

公开(公告)号：US12142574B2

公开(公告)日：2024-11-12

申请号：US17390104

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

公开(公告)号：US20240145430A1

公开(公告)日：2024-05-02

申请号：US18410060

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng

IPC: H01L23/00 ,  H01L23/528

CPC classification number: H01L24/83 ,  H01L23/5283 ,  H01L24/27 ,  H01L24/32 ,  H01L2224/27452 ,  H01L2224/2784 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/83201 ,  H01L2924/37001

Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first s

公开(公告)号：US20220310527A1

公开(公告)日：2022-09-29

申请号：US17390104

申请日：2021-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

IPC: H01L23/544 ,  H01L23/522 ,  H01L21/768

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

公开(公告)号：US20210257295A1

公开(公告)日：2021-08-19

申请号：US16906659

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Wei Chan ,  Yung-Shih Cheng ,  Wen-Sheh Huang ,  Yu-Hsiang Chen

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.

公开(公告)号：US20240395728A1

公开(公告)日：2024-11-28

申请号：US18791100

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

公开(公告)号：US12074107B2

公开(公告)日：2024-08-27

申请号：US17813880

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Wei Chan ,  Yung-Shih Cheng ,  Wen-Sheh Huang

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L21/762 ,  H01L21/76877 ,  H01L23/5226 ,  H01L28/20

Abstract: A method of forming a semiconductor device includes forming a conductive feature and a first punch stop layer, where the conductive feature has a first top surface, and where the first punch stop layer has a second top surface that is substantially level with the first top surface. The method further includes forming a resistive element over the first punch stop layer. The method further includes etching through a first portion of the resistive element to form a first trench that exposes both the second top surface of the first punch stop layer and a first sidewall surface of the resistive element. The method further includes forming a first conductive via within the first trench, where the first conductive via contacts the first sidewall surface of the resistive element.