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    MONOLITHIC COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) - INTEGRATED SILICON MICROPHONE
    1.
    发明申请
    MONOLITHIC COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) - INTEGRATED SILICON MICROPHONE 有权
    单相补充金属氧化物半导体（CMOS） - 集成硅麦克风

    公开(公告)号：US20160241979A1

    公开(公告)日：2016-08-18

    申请号：US14620368

    申请日：2015-02-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Yi Cho ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng ,  Yao-Te Huang

    IPC: H04R31/00 ,  H04R19/04

    CPC classification number: H04R1/04 ,  H04R19/005 ,  H04R19/04

    Abstract: Some embodiments relate to a manufacturing process that combines a MEMS capacitor of a microelectromechanical systems (MEMS) microphone and an integrated circuit (IC) onto a single substrate. A dielectric is formed over a device substrate. A conductive diaphragm and a conductive backplate are formed within the dielectric, with a sacrificial portion of the dielectric between them. A first recess is formed, which extends through the dielectric to an upper surface of the conductive diaphragm. A second recess is formed, which extends through the substrate and dielectric to a lower surface of the conductive backplate. The sacrificial layer is removed to create an air gap between the conductive diaphragm and the conductive backplate. The air gap joins the first and second recesses to form a cavity that extends continuously through the dielectric and the substrate. The present disclosure is also directed to the semiconductor structure of the MEMS microphone resulting from the manufacturing process.

    Abstract translation: 一些实施例涉及将微机电系统（MEMS）麦克风的MEMS电容器和集成电路（IC）组合到单个基板上的制造工艺。 在器件衬底上形成电介质。 导电隔膜和导电背板形成在电介质内，电介质的牺牲部分在它们之间。 形成第一凹部，其延伸穿过电介质到导电隔膜的上表面。 形成第二凹槽，其延伸穿过基板和电介质到导电背板的下表面。 去除牺牲层以在导电隔膜和导电背板之间产生气隙。 空气间隙连接第一和第二凹部以形成连续延伸通过电介质和基底的空腔。 本公开还涉及由制造过程产生的MEMS麦克风的半导体结构。

    Integrated Circuit Package and Method of Forming Same
    3.
    发明申请
    Integrated Circuit Package and Method of Forming Same 有权

    公开(公告)号：US20220310556A1

    公开(公告)日：2022-09-29

    申请号：US17350856

    申请日：2021-06-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng

    IPC: H01L23/00 ,  H01L23/528

    Abstract: In an embodiment, a method includes performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure; performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition; planarizing the first bonding layer; forming a second bonding layer over a second substrate; pressing the second bonding layer onto the first bonding layer; and removing the first substrate.

    Monolithic complementary metal-oxide semiconductor (CMOS)-integrated silicon microphone
    4.
    发明授权
    Monolithic complementary metal-oxide semiconductor (CMOS)-integrated silicon microphone 有权
    单片互补金属氧化物半导体（CMOS） - 集成硅麦克风

    公开(公告)号：US09462402B2

    公开(公告)日：2016-10-04

    申请号：US14620368

    申请日：2015-02-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Yi Cho ,  Chia-Hua Chu ,  Chun-Wen Cheng ,  Jung-Huei Peng ,  Yao-Te Huang

    IPC: H01R31/00 ,  H04R31/00 ,  H04R19/04

    CPC classification number: H04R1/04 ,  H04R19/005 ,  H04R19/04

    Abstract: Some embodiments relate to a manufacturing process that combines a MEMS capacitor of a microelectromechanical systems (MEMS) microphone and an integrated circuit (IC) onto a single substrate. A dielectric is formed over a device substrate. A conductive diaphragm and a conductive backplate are formed within the dielectric, with a sacrificial portion of the dielectric between them. A first recess is formed, which extends through the dielectric to an upper surface of the conductive diaphragm. A second recess is formed, which extends through the substrate and dielectric to a lower surface of the conductive backplate. The sacrificial layer is removed to create an air gap between the conductive diaphragm and the conductive backplate. The air gap joins the first and second recesses to form a cavity that extends continuously through the dielectric and the substrate. The present disclosure is also directed to the semiconductor structure of the MEMS microphone resulting from the manufacturing process.

    Abstract translation: 一些实施例涉及将微机电系统（MEMS）麦克风的MEMS电容器和集成电路（IC）组合到单个基板上的制造工艺。 在器件衬底上形成电介质。 导电隔膜和导电背板形成在电介质内，电介质的牺牲部分在它们之间。 形成第一凹部，其延伸穿过电介质到导电隔膜的上表面。 形成第二凹槽，其延伸穿过基板和电介质到导电背板的下表面。 去除牺牲层以在导电隔膜和导电背板之间产生气隙。 空气间隙连接第一和第二凹部以形成连续延伸通过电介质和基底的空腔。 本公开还涉及由制造过程产生的MEMS麦克风的半导体结构。

    Semiconductor structure and method of manufacture
    5.
    发明授权
    Semiconductor structure and method of manufacture 有权

    公开(公告)号：US12283532B2

    公开(公告)日：2025-04-22

    申请号：US17866807

    申请日：2022-07-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Te Huang ,  Liang-Chor Chung

    IPC: H01L21/66 ,  H01L21/768

    Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
    6.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE 有权

    公开(公告)号：US20240395728A1

    公开(公告)日：2024-11-28

    申请号：US18791100

    申请日：2024-07-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Te Huang ,  Hong-Wei Chan ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Hui Lee

    IPC: H01L23/544 ,  H01L21/768 ,  H01L23/522

    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming an interconnect structure over a device wafer. The device wafer includes a first integrated circuit, a semiconductor substrate, and a redistribution structure. The method further includes forming a metallization layer and a group of dummy insertion structures having a stepped pattern density in a topmost dielectric layer of the interconnect structure. The group of dummy insertion structures and the metallization layer are planarized with the dielectric layer. The method further includes forming a first bonding layer over the group of dummy insertion structures, the metallization layer, and the dielectric layer. The method further includes bonding a carrier wafer to the first bonding layer, forming an opening through the semiconductor substrate, and forming a conductive via in the opening and electrically coupled to the redistribution structure.

    Semiconductor Structure and Method of Manufacture
    9.
    发明申请
    Semiconductor Structure and Method of Manufacture 有权

    公开(公告)号：US20220352043A1

    公开(公告)日：2022-11-03

    申请号：US17866807

    申请日：2022-07-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Te Huang ,  Liang-Chor Chung

    IPC: H01L21/66 ,  H01L21/768

    Abstract: Test pad structures and methods of forming a test pad are described herein. A method for forming a test pad includes forming a device element over a substrate, depositing a dielectric layer over the device element and the substrate, and etching openings in the dielectric layer to a first depth. Once the openings have been formed, a conductive material is deposited in the openings and followed by a chemical mechanical planarization to form a first grid feature and a panel region of the test pad, the first grid feature extending lengthwise from the panel region to a perimeter of the test pad. Once formed, a probe may be used to contact the panel region of the test pad during a wafer acceptance test (WAT) and/or a process control monitoring (PCM) test of the device element.

    Increasing Contact Areas of Contacts for MIM Capacitors
    10.
    发明申请
    Increasing Contact Areas of Contacts for MIM Capacitors 有权

    公开(公告)号：US20220328398A1

    公开(公告)日：2022-10-13

    申请号：US17809938

    申请日：2022-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yao-Te Huang ,  Yung-Shih Cheng

    IPC: H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01L21/768 ,  H01L21/308

    Abstract: A method includes forming a first electrode layer having a first opening, with the first opening having a first lateral dimension, forming a first capacitor insulator over the first electrode layer, and forming a second electrode layer over the first capacitor insulator, with the second electrode layer having a second opening. The first opening is directly underlying the second opening. The second opening has a second lateral dimension greater than the first lateral dimension. The method further includes depositing a dielectric layer over the second electrode layer, and forming a contact opening, which comprises a first portion including the first opening, and a second portion including the second opening. A conductive plug is formed in the contact opening.

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