公开(公告)号：US11355410B2

公开(公告)日：2022-06-07

申请号：US16927624

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Sheh Huang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/367 ,  H01L23/528 ,  H01L49/02 ,  H01L23/31 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

公开(公告)号：US20210257295A1

公开(公告)日：2021-08-19

申请号：US16906659

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Wei Chan ,  Yung-Shih Cheng ,  Wen-Sheh Huang ,  Yu-Hsiang Chen

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a low-k dielectric layer over the second dielectric layer, a second dielectric layer on the high resistance layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.

公开(公告)号：US10985011B2

公开(公告)日：2021-04-20

申请号：US15866022

申请日：2018-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Wen Hsueh ,  Yu-Hsiang Chen ,  Wen-Sheh Huang ,  Chii-Ping Chen ,  Wan-Te Chen

IPC: H01L21/02 ,  H01L21/762 ,  H01L27/06 ,  H01L23/64 ,  H01L21/304 ,  H01L27/08 ,  H01L23/522 ,  H01L49/02 ,  H01L23/528

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.

公开(公告)号：US12165947B2

公开(公告)日：2024-12-10

申请号：US17217868

申请日：2021-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Sheh Huang ,  Yung-Shih Cheng ,  Jiing-Feng Yang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a transistor over a front side of a substrate, in which the transistor comprises a channel region, a gate region over the channel region, and source/drain regions on opposite sides of the gate region; forming a front-side interconnect structure over the transistor, wherein the front-side interconnect structure includes a dielectric layer and conductive features; and bonding the front-side interconnect structure to a carrier substrate via a bonding layer, in which the bonding layer is between the front-side interconnect structure and the carrier substrate, and the bonding layer has a higher thermal conductivity than the dielectric layer of the front-side interconnect structure.

公开(公告)号：US11923295B2

公开(公告)日：2024-03-05

申请号：US16906659

申请日：2020-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Wei Chan ,  Yung-Shih Cheng ,  Wen-Sheh Huang ,  Yu-Hsiang Chen

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5228 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226

Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.

公开(公告)号：US20210335690A1

公开(公告)日：2021-10-28

申请号：US16927624

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Sheh Huang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/367 ,  H01L27/092 ,  H01L23/528 ,  H01L49/02 ,  H01L23/31 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/06

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

公开(公告)号：US10515852B2

公开(公告)日：2019-12-24

申请号：US15865845

申请日：2018-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Sheh Huang ,  Hsiu-Wen Hsueh ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L21/768 ,  H01L21/762 ,  H01L27/06 ,  H01L21/311

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element electrically connected to the conductive feature. A first portion of the resistive element is over the dielectric layer, and a second portion of the resistive element extends towards the conductive feature.

公开(公告)号：US20240194559A1

公开(公告)日：2024-06-13

申请号：US18583411

申请日：2024-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Sheh Huang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/367 ,  H01L21/8238 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L23/367 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0922 ,  H01L28/10 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L2224/0401

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

公开(公告)号：US11942390B2

公开(公告)日：2024-03-26

申请号：US17833288

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Sheh Huang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/367 ,  H01L21/8238 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L23/367 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0922 ,  H01L28/10 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L2224/0401

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

公开(公告)号：US20220310472A1

公开(公告)日：2022-09-29

申请号：US17833288

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Sheh Huang ,  Yu-Hsiang Chen ,  Chii-Ping Chen

IPC: H01L23/367 ,  H01L23/528 ,  H01L49/02 ,  H01L23/31 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/775 ,  H01L29/06 ,  H01L27/092

Abstract: A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.