公开(公告)号：US08903030B2

公开(公告)日：2014-12-02

申请号：US13670519

申请日：2012-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tao Wen Chung ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Chih-Chang Lin ,  Yuwen Swei ,  Tsung-Ching Huang

IPC: H04L7/00 ,  H04L7/027

CPC classification number: H04L7/0331

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract translation: 时钟数据恢复电路（CDR）从串行比特流中提取比特数据值而不参考发射机时钟。 可控振荡器产生受控的再生时钟信号以匹配位之间的转换的频率和相位，并且在最佳相位对串行数据进行采样。 相位检测器产生用于时钟相对于数据转换时间的早期或晚期指示位，其被积累并应用于具有用于频率和相位的两个不同反馈路径的二阶反馈控制，被组合以校正可控振荡器， 相位和/或确定比特流数据值被采样的最佳相位。 二阶滤波器以不同的速率操作，使得相位校正具有短到一个时钟周期的等待时间，并且频率校正等待时间在多个周期内发生。