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公开(公告)号：US11841561B2
公开(公告)日：2023-12-12
申请号：US17379620
申请日：2021-07-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Chan-Hong Chern , Chih-Chang Lin
CPC classification number: G02F1/025 , G02F1/2255 , G02F1/2257 , G02F2201/508 , G02F2201/58
Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.
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公开(公告)号：US11531159B2
公开(公告)日：2022-12-20
申请号：US17212934
申请日：2021-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Lan-Chou Cho , Huan-Neng Chen , Min-Hsiang Hsu , Feng-Wei Kuo , Chih-Chang Lin , Weiwei Song , Chewn-Pu Jou
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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公开(公告)号：US20210396930A1
公开(公告)日：2021-12-23
申请号：US17212934
申请日：2021-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Lan-Chou Cho , Huan-Neng Chen , Min Hsiang Hsu , Feng-Wei Kuo , Chih-Chang Lin , Weiwei Song , Chewn-Pu Jou
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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公开(公告)号：US20140270031A1
公开(公告)日：2014-09-18
申请号：US14164399
申请日：2014-01-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen (David) Chung , Tsung-Ching (Jim) Huang , Chih-Chang Lin
IPC: H04L7/00
CPC classification number: H04L7/0025 , H03L7/0812
Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.
Abstract translation: 一些实施例涉及相位插值器。 相位内插器包括控制块，用于提供多个相位插值控制信号，这些相位插值控制信号被共同指示第一时钟和第二时钟之间的相位差。 相位插值控制信号限定不同的相位步长，通过该相位步长第一时钟将被相移以限制相位差。 多个吉尔伯特单元基于多个相位插值控制信号分别提供多个电流电平。 多个电流控制元件从多个吉尔伯特单元调整多个电流电平。 对于不同的相位步长，多个电流水平被不同的量调节。
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公开(公告)号：US12228768B2
公开(公告)日：2025-02-18
申请号：US18063186
申请日：2022-12-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Chih-Chang Lin , Stefan Rusu , Min-Hsiang Hsu
Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
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Patent Agency Ranking
公开(公告)号：US20230375862A1
公开(公告)日：2023-11-23
申请号：US18363489
申请日：2023-08-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Stefan Rusu , Chan-Hong Chern , Chih-Chang Lin
CPC classification number: G02F1/025 , G02F1/2255 , G02F1/2257 , G02F2201/508 , G02F2201/58
Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.
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公开(公告)号：US11525957B2
公开(公告)日：2022-12-13
申请号：US17150628
申请日：2021-01-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Weiwei Song , Chan-Hong Chern , Chih-Chang Lin , Stefan Rusu , Min-Hsiang Hsu
Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
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公开(公告)号：US09503252B2
公开(公告)日：2016-11-22
申请号：US14164399
申请日：2014-01-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming-Chieh Huang , Chan-Hong Chern , Tao Wen (David) Chung , Tsung-Ching (Jim) Huang , Chih-Chang Lin
CPC classification number: H04L7/0025 , H03L7/0812
Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.
Abstract translation: 一些实施例涉及相位插值器。 相位插值器包括一个控制块，用于提供多个相位插值控制信号，这些相位插值控制信号集中表示第一时钟和第二时钟之间的相位差。 相位插值控制信号限定不同的相位步长，通过该相位步长第一时钟将被相移以限制相位差。 多个吉尔伯特单元基于多个相位插值控制信号分别提供多个电流电平。 多个电流控制元件从多个吉尔伯特单元调整多个电流电平。 对于不同的相位步长，多个电流水平被不同的量调节。
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公开(公告)号：US09391626B2
公开(公告)日：2016-07-12
申请号：US14456064
申请日：2014-08-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Tao Wen Chung , Ming-Chieh Huang , Chih-Chang Lin , Tsung-Ching Huang , Fu-Lung Hsueh
CPC classification number: H03L7/103 , H03L7/097 , H03L7/0995 , H03L7/1072 , H03L7/18 , H03L2207/06
Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
Abstract translation: 电路包括电容负载压控振荡器，其具有被配置为接收第一输入信号的输入和被配置为输出振荡输出信号的输出。 校准电路耦合到压控振荡器，并被配置为将一个或多个控制信号输出到电容负载压控振荡器，用于调整振荡输出信号的频率。 校准电路被配置为响应于输入电压与至少一个参考电压的比较而输出一个或多个控制信号。
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公开(公告)号：US12276836B2
公开(公告)日：2025-04-15
申请号：US18078793
申请日：2022-12-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chan-Hong Chern , Chih-Chang Lin , Min-Hsiang Hsu , Weiwei Song , Chewn-Pu Jou , Feng-Wei Kuo , Huan-Neng Chen , Lan-Chou Cho
Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the first waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
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