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公开(公告)号:US20240363425A1
公开(公告)日:2024-10-31
申请号:US18769679
申请日:2024-07-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L21/8234 , H01L21/02 , H01L21/3065 , H01L27/088 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66
CPC classification number: H01L21/823462 , H01L21/02532 , H01L21/3065 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66795 , H01L27/088
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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公开(公告)号:US20230326990A1
公开(公告)日:2023-10-12
申请号:US18334918
申请日:2023-06-14
Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L29/423 , H01L21/8234 , H01L29/66 , H01L29/10 , H01L21/02 , H01L21/3065 , H01L27/088 , H01L29/06
CPC classification number: H01L29/42392 , H01L21/823412 , H01L29/66795 , H01L29/1037 , H01L21/02532 , H01L21/3065 , H01L21/823437 , H01L21/823431 , H01L27/0886 , H01L29/0673 , H01L21/823462 , H01L27/088
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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公开(公告)号:US20220181214A1
公开(公告)日:2022-06-09
申请号:US17682604
申请日:2022-02-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L21/8234 , H01L21/02 , H01L21/3065 , H01L29/66 , H01L27/088 , H01L29/06 , H01L29/10
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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公开(公告)号:US11715779B2
公开(公告)日:2023-08-01
申请号:US17682604
申请日:2022-02-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L29/423 , H01L21/8234 , H01L29/66 , H01L29/10 , H01L21/02 , H01L21/3065 , H01L27/088 , H01L29/06
CPC classification number: H01L29/42392 , H01L21/02532 , H01L21/3065 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L27/0886 , H01L29/0673 , H01L29/1037 , H01L29/66795 , H01L27/088
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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公开(公告)号:US12087638B2
公开(公告)日:2024-09-10
申请号:US18334918
申请日:2023-06-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L21/8234 , H01L21/02 , H01L21/3065 , H01L27/088 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/66
CPC classification number: H01L21/823462 , H01L21/02532 , H01L21/3065 , H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L29/0673 , H01L29/1037 , H01L29/42392 , H01L29/66795 , H01L27/088
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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公开(公告)号:US20210375683A1
公开(公告)日:2021-12-02
申请号:US16888239
申请日:2020-05-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L21/8234 , H01L29/66 , H01L29/10 , H01L21/02 , H01L29/06 , H01L27/088 , H01L21/3065
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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公开(公告)号:US11264283B2
公开(公告)日:2022-03-01
申请号:US16888239
申请日:2020-05-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shih-Yao Lin , Chih-Chung Chiu , Kuei-Yu Kao , Chen-Ping Chen , Chih-Han Lin
IPC: H01L21/8234 , H01L29/66 , H01L29/10 , H01L21/02 , H01L21/3065 , H01L27/088 , H01L29/06
Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.
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