公开(公告)号：US20230064078A1

公开(公告)日：2023-03-02

申请号：US17460699

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin Chu Liang ,  Hung-Yao Chen ,  Pei-Ren Jeng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/027

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

公开(公告)号：US20230317831A1

公开(公告)日：2023-10-05

申请号：US18331355

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Pin Chu Liang ,  Hung-Yao Chen ,  Pei-Ren Jeng

IPC: H01L29/66 ,  H01L21/027 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L29/66636 ,  H01L21/0274 ,  H01L29/7855 ,  H01L21/02532

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

公开(公告)号：US11710781B2

公开(公告)日：2023-07-25

申请号：US17460699

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin Chu Liang ,  Hung-Yao Chen ,  Pei-Ren Jeng

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/027 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/0274 ,  H01L21/02532 ,  H01L29/66636 ,  H01L29/7855

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.