公开(公告)号：US12170228B2

公开(公告)日：2024-12-17

申请号：US18366864

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Yao Chen ,  Pin-Chu Liang ,  Hsueh-Chang Sung ,  Pei-Ren Jeng ,  Yee-Chia Yeo

IPC: H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first thickness.

公开(公告)号：US12087845B2

公开(公告)日：2024-09-10

申请号：US17236535

申请日：2021-04-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ao Chang ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L29/66 ,  H01L21/67 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/67017 ,  H01L21/823431

Abstract: A system and methods of manufacturing semiconductor devices is described herein. The method includes forming a recess between fins in a substrate and forming a dielectric layer over the fins and in the recess. Once the dielectric layer has been formed, a bottom seed structure is formed over the dielectric layer within the recess and the dielectric layer is exposed along sidewalls of the recess. A dummy gate material is grown from the bottom seed structure in a bottom-up deposition process without growing the dummy gate material from the dielectric layer exposed along sidewalls of the recess.

公开(公告)号：US12002854B2

公开(公告)日：2024-06-04

申请号：US17520983

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

公开(公告)号：US11798984B2

公开(公告)日：2023-10-24

申请号：US17588478

申请日：2022-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Chun Huang ,  Bor Chiuan Hsieh ,  Pei-Ren Jeng ,  Tai-Chun Huang ,  Tze-Liang Lee

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/76227 ,  H01L29/66795

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

公开(公告)号：US20230317831A1

公开(公告)日：2023-10-05

申请号：US18331355

申请日：2023-06-08

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Pin Chu Liang ,  Hung-Yao Chen ,  Pei-Ren Jeng

IPC: H01L29/66 ,  H01L21/027 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/6681 ,  H01L29/66636 ,  H01L21/0274 ,  H01L29/7855 ,  H01L21/02532

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

公开(公告)号：US11710781B2

公开(公告)日：2023-07-25

申请号：US17460699

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin Chu Liang ,  Hung-Yao Chen ,  Pei-Ren Jeng

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/027 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/0274 ,  H01L21/02532 ,  H01L29/66636 ,  H01L29/7855

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

公开(公告)号：US11710777B2

公开(公告)日：2023-07-25

申请号：US17081675

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ao Chang ,  De-Wei Yu ,  Chii-Horng Li ,  Yee-Chia Yeo ,  Hsueh-Chang Sung ,  Pei-Ren Jeng

IPC: H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/02071 ,  H01L21/32135 ,  H01L29/66795

Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

公开(公告)号：US20220415715A1

公开(公告)日：2022-12-29

申请号：US17490922

申请日：2021-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jeng-Wei Yu ,  Yi-Fang Pai ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Yee-Chia Yeo

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/66

Abstract: A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

公开(公告)号：US20220336640A1

公开(公告)日：2022-10-20

申请号：US17351679

申请日：2021-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Ku Chen ,  Ji-Yin Tsai ,  Jeng-Wei Yu ,  Yi-Fang Pai ,  Pei-Ren Jeng ,  Yee-Chia Yeo ,  Chii-Horng Li

IPC: H01L29/66 ,  H01L21/762

Abstract: A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

公开(公告)号：US11367660B2

公开(公告)日：2022-06-21

申请号：US17121490

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Hsiung Yen ,  Ta-Chun Ma ,  Chien-Chang Su ,  Jung-Jen Chen ,  Pei-Ren Jeng ,  Chii-Horng Li ,  Kei-Wei Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L21/324 ,  H01L27/092

Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.