公开(公告)号：US09831307B2

公开(公告)日：2017-11-28

申请号：US15370244

申请日：2016-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chang Chen ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/76 ,  H01L21/762 ,  H01L29/165

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.

公开(公告)号：US20170084689A1

公开(公告)日：2017-03-23

申请号：US15370244

申请日：2016-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chang Chen ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.

公开(公告)号：US09536771B2

公开(公告)日：2017-01-03

申请号：US13860765

申请日：2013-04-11

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Po-Chang Chen ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L29/66 ,  H01L27/02 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.

Abstract translation: 本公开内容涉及具有由可流动介电材料分离的结构的晶体管的集成芯片IC以及相关的形成方法。 在一些实施例中，集成芯片具有半导体衬底和嵌入硅锗（SiGe）区域，该半导体衬底和半导体衬底上的位置从半导体衬底内的位置以正电位延伸。 第一栅极结构位于通过第一间隙与嵌入的SiGe区分离的位置。 在栅极结构和嵌入的SiGe区域之间设置可流动介电材料，以及设置在可流动介电材料之上的预金属电介质（PMD）层。 可流动介电材料提供良好的间隙填充能力，以减轻相邻栅极结构之间的间隙填充期间的空隙形成。

公开(公告)号：US20140306294A1

公开(公告)日：2014-10-16

申请号：US13860765

申请日：2013-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Po-Chang Chen ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/762 ,  H01L29/06

CPC classification number: H01L29/0653 ,  H01L21/0214 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/762 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures.

Abstract translation: 本公开内容涉及具有由可流动介电材料分离的结构的晶体管的集成芯片IC以及相关的形成方法。 在一些实施例中，集成芯片具有半导体衬底和嵌入硅锗（SiGe）区域，该半导体衬底和半导体衬底上的位置从半导体衬底内的位置以正电位延伸。 第一栅极结构位于通过第一间隙与嵌入的SiGe区分离的位置。 在栅极结构和嵌入的SiGe区域之间设置可流动介电材料，以及设置在可流动介电材料之上的预金属电介质（PMD）层。 可流动介电材料提供良好的间隙填充能力，以减轻相邻栅极结构之间的间隙填充期间的空隙形成。