公开(公告)号：US20240258160A1

公开(公告)日：2024-08-01

申请号：US18609908

申请日：2024-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-Nan Lin ,  Chia-Yu Wu ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  C23F1/12 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76829 ,  C23F1/12 ,  H01L21/02178 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53295

Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.

公开(公告)号：US10749004B2

公开(公告)日：2020-08-18

申请号：US16009925

申请日：2018-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/12 ,  H01L21/00 ,  H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US10164063B2

公开(公告)日：2018-12-25

申请号：US15434343

申请日：2017-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Chiang ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L29/78 ,  H01L21/82 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L27/088 ,  H01L21/8234

Abstract: The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.

公开(公告)号：US09859137B2

公开(公告)日：2018-01-02

申请号：US14291555

申请日：2014-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Cha Kuo ,  Wen-Long Lee ,  Tzu-Chien Cheng ,  Ding-I Liu

IPC: H01L21/67 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L21/67109 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/32139 ,  H01L21/67115 ,  H01L21/6715 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for forming a semiconductor device structure and an apparatus for heating a semiconductor substrate are provided. The method includes spin coating a material layer over a semiconductor substrate. The method also includes heating the material layer by using a first heater above the semiconductor substrate and a second heater below the semiconductor substrate.

公开(公告)号：US09209071B2

公开(公告)日：2015-12-08

申请号：US14229264

申请日：2014-03-28

Applicant: Taiwan Semiconductor Manufacturing CO., LTD.

Inventor： Geng-Shuoh Chang ,  Chun-Sheng Wu ,  Chun-Li Lin ,  Yi-Fang Li ,  Po-Hsiung Leu ,  Ding-I Liu

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric layer formed over the semiconductor substrate, a first anti-etch layer, a second anti-etch layer and a conductive material. The dielectric layer has an opening. The first anti-etch layer is formed on the sidewall of the opening and made of a material having resistance to peroxide. The second anti-etch layer is formed over the first anti-etch layer and made of a material having resistance to acid. The conductive material is formed within the opening and in contact with the second anti-etch layer.

Abstract translation: 半导体结构包括半导体衬底，形成在半导体衬底上的电介质层，第一抗蚀刻层，第二抗蚀刻层和导电材料。 电介质层具有开口。 第一抗蚀刻层形成在开口的侧壁上并由具有过氧化物的材料制成。 第二抗蚀刻层形成在第一抗蚀刻层上并由耐酸性的材料制成。 导电材料形成在开口内并与第二抗蚀刻层接触。

公开(公告)号：US11322397B2

公开(公告)日：2022-05-03

申请号：US16664317

申请日：2019-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsiao-Min Chen ,  Jyh-Nan Lin ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L21/02

Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.

公开(公告)号：US11264467B2

公开(公告)日：2022-03-01

申请号：US16985276

申请日：2020-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Ding-I Liu ,  Yuh-Ta Fan

IPC: H01L29/12 ,  H01L21/00 ,  H01L29/26 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a metal layer, an insulating layer disposed above the metal layer, and a multi-layer diffusion barrier disposed on the metal layer between the metal layer and the insulating layer. The multi-layer diffusion barrier includes a first material layer including a metallic nitride and a second material layer including a metallic oxide.

公开(公告)号：US11069534B2

公开(公告)日：2021-07-20

申请号：US16653313

申请日：2019-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-An Han ,  Ding-I Liu ,  Yuh-Ta Fan ,  Kai-Shiung Hsu

IPC: H01L21/3213 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78 ,  H01L21/285 ,  H01L21/3215 ,  H01L29/66

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.

公开(公告)号：US10978337B2

公开(公告)日：2021-04-13

申请号：US16550901

申请日：2019-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-nan Lin ,  Mu-Min Hung ,  Kai-Shiung Hsu ,  Ding-I Liu

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  C23C16/455 ,  C23C16/34

Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.

公开(公告)号：US10533252B2

公开(公告)日：2020-01-14

申请号：US15088064

申请日：2016-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Chiu ,  Ding-I Liu ,  Chin-Feng Lin ,  Po-Hsiung Leu

IPC: C23C16/50 ,  C23C16/455 ,  H01J37/32 ,  C23C16/505

Abstract: A showerhead is configured to be mounted inside a processing chamber and provide a processing gas onto a semiconductor wafer inside the processing chamber. The showerhead includes a supply plenum, a faceplate, and an electrode plate assembly. The faceplate is disposed at a side of the supply plenum. The electrode plate assembly is disposed between a gas source and the supply plenum. The electrode plate assembly includes a first plate having a unitary construction and having a plurality of first gas holes, and a second plate having a unitary construction and having a plurality of second gas holes. The second plate is located between the first plate and the supply plenum and separated from the first plate. The plurality of second gas holes are partially overlapped but misaligned with the plurality of first gas holes. A semiconductor apparatus having the same and a semiconductor process are also provided.