公开(公告)号：US20240249934A1

公开(公告)日：2024-07-25

申请号：US18626864

申请日：2024-04-04

申请人： Applied Materials, Inc.

发明人： Naomi Yoshida ,  Bhaskar Jyoti Bhuyan ,  Hsueh Chung Chen ,  Scott A. DeVries ,  Raghuveer Satya Makala

IPC分类号： H01L21/02 ,  C23C16/455 ,  H01L21/768

CPC分类号： H01L21/0217 ,  C23C16/45544 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02326 ,  H01L21/76831 ,  H01L21/02046 ,  H01L21/02052

摘要： Methods of manufacturing electronic devices, e.g., logic devices or memory devices, are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; pre-treating the top surface of the film stack to form a treated surface; exposing the treated surface to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

公开(公告)号：US20240154026A1

公开(公告)日：2024-05-09

申请号：US18414469

申请日：2024-01-17

申请人： Marlin Semiconductor Limited

发明人： Te-Chang Hsu ,  Chun-Chia Chen ,  Yao-Jhan Wang

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/768

CPC分类号： H01L29/66545 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/31053 ,  H01L21/3115 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/41791

摘要： A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

公开(公告)号：US11955333B2

公开(公告)日：2024-04-09

申请号：US17208719

申请日：2021-03-22

申请人： Applied Materials, Inc.

发明人： Jethro Tannos ,  Bhargav Sridhar Citla ,  Srinivas D. Nemani ,  Ellie Yieh ,  Joshua Alan Rubnitz ,  Erica Chen ,  Soham Sunjay Asrani ,  Nikolaos Bekiaris ,  Douglas Arthur Buchberger, Jr.

IPC分类号： H01J37/32 ,  C23C16/40 ,  C23C16/458 ,  C23C16/505 ,  C23C16/52 ,  C23C16/56 ,  H01L21/02

CPC分类号： H01L21/02326 ,  C23C16/401 ,  C23C16/4584 ,  C23C16/505 ,  C23C16/52 ,  C23C16/56 ,  H01J37/32174 ,  H01J37/32357 ,  H01J37/32449 ,  H01J37/32724 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/02274 ,  H01J2237/20214 ,  H01J2237/3321

摘要： Methods and apparatus for processing a substrate are provided herein. For example, a method includes supplying a vaporized precursor into a processing volume, supplying activated elements including ions and radicals from a remote plasma source, energizing the activated elements using RF source power at a first duty cycle to react with the vaporized precursor to deposit an SiNHx film onto a substrate disposed in the processing volume, supplying a first process gas from the remote plasma source while providing RF bias power at a second duty cycle different from the first duty cycle to the substrate support to convert the SiNHx film to an SiOx film, supplying a process gas mixture formed from a second process gas supplied from the remote plasma source and a third process gas supplied from the gas supply while providing RF bias power at the second duty cycle to the substrate support, and annealing the substrate.

公开(公告)号：US11917827B2

公开(公告)日：2024-02-27

申请号：US17648719

申请日：2022-01-24

申请人： Kioxia Corporation

发明人： Naoki Yasuda

IPC分类号： H01L27/1157 ,  H01L21/02 ,  H01L21/28 ,  H01L29/10 ,  H01L29/423 ,  H01L29/51 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/35 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02326 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518 ,  H10B43/10 ,  H10B43/27 ,  H01L21/02252 ,  H01L21/02255

摘要： According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

公开(公告)号：US11908921B2

公开(公告)日：2024-02-20

申请号：US17412896

申请日：2021-08-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Yun Peng ,  Fu-Ting Yen ,  Keng-Chu Lin

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L29/66553 ,  H01L29/0653 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66742 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02167 ,  H01L21/02208 ,  H01L21/02219 ,  H01L21/02326 ,  H01L21/02348 ,  H01L21/31111 ,  H01L29/78696

摘要： The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.

公开(公告)号：US11823897B2

公开(公告)日：2023-11-21

申请号：US17697311

申请日：2022-03-17

申请人： TOKYO ELECTRON LIMITED

发明人： Makoto Muramatsu ,  Hisashi Genjima

IPC分类号： C23C18/14 ,  H01L21/02

CPC分类号： H01L21/02348 ,  C23C18/143 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02323 ,  H01L21/02326

摘要： There is provided a technique of forming an insulating film containing silicon oxide. A coating solution containing polysilazane is applied onto a wafer W, the solvent of the coating solution is volatilized, and the coating film is irradiated with ultraviolet rays in nitrogen atmosphere before performing a curing process. Dangling bonds are generated in silicon which is a pre-hydrolyzed site in polysilazane. Therefore, the energy for hydrolysis is reduced, and unhydrolyzed sites are reduced even when the temperature of the curing process is 350° C. Since efficient dehydration condensation occurs, the crosslinking rate is improved, and a dense (good-quality) insulation film is formed. By forming a protective film on the surface of the coating film to which ultraviolet rays irradiated, the reaction of dangling bonds prior to the curing process is suppressed.

公开(公告)号：US20180254279A1

公开(公告)日：2018-09-06

申请号：US15967930

申请日：2018-05-01

申请人： Toshiba Memory Corporation

发明人： Naoki Yasuda

IPC分类号： H01L27/1157 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11582 ,  H01L29/51 ,  H01L27/11565 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L27/1157 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/02326 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/518

摘要： According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode members and a plurality of insulating members, each of the electrode members and each of the insulating members being stacked alternately in a first direction on the substrate. The semiconductor memory device also includes a memory hole that extends in the stacked body in the first direction and a semiconductor member that is disposed to extend in the memory hole in the first direction. The semiconductor memory device also includes a memory member that is disposed between the semiconductor member and the plurality of electrode members. The plurality of electrode members including a first electrode member and a second electrode member, a thickness of the memory member at the position of the first electrode member being greater than a thickness of the memory member at the position of the second electrode member.

公开(公告)号：US20180201807A1

公开(公告)日：2018-07-19

申请号：US15856659

申请日：2017-12-28

申请人： TOKYO OHKA KOGYO CO., LTD.

发明人： Yasushi FUJII ,  Kunihiro NODA ,  Hiroki CHISAKA ,  Kazuya SOMEYA ,  Koichi MISUMI ,  Dai SHIOTA

IPC分类号： C09D183/16 ,  C08G77/62 ,  H01L21/02

CPC分类号： C09D183/16 ,  C08G77/62 ,  C08L83/16 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/02326 ,  H01L21/02337

摘要： A composition capable of stably providing a high-quality siliceous film even under relatively low-temperature heating conditions, and a method of using the composition for forming a siliceous film. The composition includes a polysilazane and an imidazole group-containing compound represented by Formula (B):

公开(公告)号：US09991154B2

公开(公告)日：2018-06-05

申请号：US15054113

申请日：2016-02-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Ken Lin ,  Jia-Ming Lin ,  Hsien-Che Teng ,  Yung-Chou Shih ,  Kun-Dian She ,  Lichia Yang ,  Yun-Wen Chu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02236 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L29/66795 ,  H01L29/7848

摘要： A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.

公开(公告)号：US09892927B2

公开(公告)日：2018-02-13

申请号：US15443151

申请日：2017-02-27

申请人： Texas Instruments Incorporated

发明人： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC分类号： H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01J37/32 ,  C23C16/458 ,  C23C16/455

CPC分类号： H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

摘要： Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.