公开(公告)号：US11658119B2

公开(公告)日：2023-05-23

申请号：US17196174

申请日：2021-03-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Yi-Hsun Chiu ,  Yi-Bo Liao ,  Kuan-Lun Cheng ,  Wei-Cheng Lin ,  Wei-An Lai ,  Ming Chian Tsai ,  Jiann-Tyng Tzeng ,  Hou-Yu Chen ,  Chun-Yuan Chen ,  Huan-Chieh Su

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/78

摘要： A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.

公开(公告)号：US20230307365A1

公开(公告)日：2023-09-28

申请号：US18319593

申请日：2023-05-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Xuan Huang ,  Ching-Wei Tsai ,  Yi-Hsun Chiu ,  Yi-Bo Liao ,  Kuan-Lun Cheng ,  Wei-Cheng Lin ,  Wei-An Lai ,  Ming Chian Tsai ,  Jiann-Tyng Tzeng ,  Hou-Yu Chen ,  Chun-Yuan Chen ,  Huan-Chieh Su

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L21/76838 ,  H01L23/5226 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/78

摘要： A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.