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公开(公告)号:US20240363702A1
公开(公告)日:2024-10-31
申请号:US18769646
申请日:2024-07-11
发明人: Yu-Xuan Huang , Wang-Chun Huang , Yi-Bo Liao , Cheng-Ting Chung , Hou-Yu Chen , Kuan-Lun Cheng , Wei Ju Lee
IPC分类号: H01L29/417 , H01L29/08 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/786
CPC分类号: H01L29/41733 , H01L29/0847 , H01L29/401 , H01L29/66742 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/78618 , H01L29/78696
摘要: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
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公开(公告)号:US11996332B2
公开(公告)日:2024-05-28
申请号:US18180140
申请日:2023-03-08
发明人: Kuan-Ting Pan , Chih-Hao Wang , Kuo-Cheng Chiang , Yi-Bo Liao , Yi-Ruei Jhan
IPC分类号: H01L21/8234 , H01L21/762 , H01L29/423
CPC分类号: H01L21/823418 , H01L21/76205 , H01L29/42384
摘要: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.
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公开(公告)号:US12094938B2
公开(公告)日:2024-09-17
申请号:US17460847
申请日:2021-08-30
发明人: Yu-Xuan Huang , Wang-Chun Huang , Yi-Bo Liao , Cheng-Ting Chung , Hou-Yu Chen , Kuan-Lun Cheng , Wei Ju Lee
IPC分类号: H01L29/41 , H01L29/08 , H01L29/40 , H01L29/417 , H01L29/66 , H01L29/423 , H01L29/45 , H01L29/786
CPC分类号: H01L29/41733 , H01L29/0847 , H01L29/401 , H01L29/66742 , H01L29/42392 , H01L29/45 , H01L29/66545 , H01L29/78618 , H01L29/78696
摘要: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
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公开(公告)号:US11031298B2
公开(公告)日:2021-06-08
申请号:US16504786
申请日:2019-07-08
发明人: Yi-Bo Liao , Kai-Chieh Yang , Ching-Wei Tsai , Kuan-Lun Cheng
IPC分类号: H01L21/8238 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/786 , H01L29/66 , H01L21/02 , H01L21/28 , H01L21/306 , H01L21/3065 , H01L27/092
摘要: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.
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公开(公告)号:US11705488B2
公开(公告)日:2023-07-18
申请号:US17576645
申请日:2022-01-14
发明人: Cheng-Ting Chung , Yu-Xuan Huang , Yi-Bo Liao , Ching-Wei Tsai , Kuan-Lun Cheng
IPC分类号: H01L29/08 , H01L29/66 , H01L21/8234 , H01L29/06
CPC分类号: H01L29/0843 , H01L21/823418 , H01L21/823431 , H01L29/0665 , H01L29/6656 , H01L29/6681
摘要: A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature.
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公开(公告)号:US20230223305A1
公开(公告)日:2023-07-13
申请号:US18180140
申请日:2023-03-08
发明人: Kuan-Ting Pan , Chih-Hao Wang , Kuo-Cheng Chiang , Yi-Bo Liao , Yi-Ruei Jhan
IPC分类号: H01L21/8234 , H01L29/423 , H01L21/762
CPC分类号: H01L21/823418 , H01L21/76205 , H01L29/42384
摘要: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.
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公开(公告)号:US11658119B2
公开(公告)日:2023-05-23
申请号:US17196174
申请日:2021-03-09
发明人: Yu-Xuan Huang , Ching-Wei Tsai , Yi-Hsun Chiu , Yi-Bo Liao , Kuan-Lun Cheng , Wei-Cheng Lin , Wei-An Lai , Ming Chian Tsai , Jiann-Tyng Tzeng , Hou-Yu Chen , Chun-Yuan Chen , Huan-Chieh Su
IPC分类号: H01L23/528 , H01L21/768 , H01L29/78 , H01L29/06 , H01L27/088 , H01L23/522
CPC分类号: H01L23/5286 , H01L21/76838 , H01L23/5226 , H01L27/088 , H01L29/0649 , H01L29/78
摘要: A semiconductor structure includes a first transistor having a first source/drain (S/D) feature and a first gate; a second transistor having a second S/D feature and a second gate; a multi-layer interconnection disposed over the first and the second transistors; a signal interconnection under the first and the second transistors; and a power rail under the signal interconnection and electrically isolated from the signal interconnection, wherein the signal interconnection electrically connects one of the first S/D feature and the first gate to one of the second S/D feature and the second gate.
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公开(公告)号:US20230064635A1
公开(公告)日:2023-03-02
申请号:US17460847
申请日:2021-08-30
发明人: Yu-Xuan Huang , Wang-Chun Huang , Yi-Bo Liao , Cheng-Ting Chung , Hou-Yu Chen , Kuan-Lun Cheng , Wei Ju Lee
IPC分类号: H01L29/417 , H01L29/08 , H01L29/66 , H01L29/40
摘要: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
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公开(公告)号:US20220140078A1
公开(公告)日:2022-05-05
申请号:US17576645
申请日:2022-01-14
发明人: Cheng-Ting Chung , Yu-Xuan Huang , Yi-Bo Liao , Ching-Wei Tsai , Kuan-Lun Cheng
IPC分类号: H01L29/08 , H01L29/66 , H01L21/8234 , H01L29/06
摘要: A device includes a semiconductor substrate, a source feature and a drain feature over the semiconductor substrate, a stack of semiconductor layers interposed between the source feature and the drain feature, a gate portion, and an inner spacer of a dielectric material. The gate portion is between two vertically adjacent layers of the stack of semiconductor layers and between the source feature and the drain feature. Moreover, the gate portion has a first sidewall surface and a second sidewall surface opposing the first sidewall surface. The inner spacer is on the first sidewall surface and between the gate portion and the drain feature. The second sidewall surface is in direct contact with the source feature.
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公开(公告)号:US20240014042A1
公开(公告)日:2024-01-11
申请号:US17861236
申请日:2022-07-10
发明人: Meng-Yu Lin , Chun-Fu Cheng , Cheng-Yin Wang , Yi-Bo Liao , Szuya Liao
IPC分类号: H01L21/28 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/775 , H01L21/3213 , H01L21/822 , H01L21/8238 , H01L29/66
CPC分类号: H01L21/28123 , H01L27/0922 , H01L29/0673 , H01L29/42392 , H01L29/78696 , H01L29/775 , H01L21/32134 , H01L21/32135 , H01L21/32139 , H01L21/8221 , H01L21/823828 , H01L21/823871 , H01L29/66742 , H01L29/66439
摘要: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.
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