公开(公告)号：US12218057B2

公开(公告)日：2025-02-04

申请号：US17241785

申请日：2021-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shih-Wei Peng ,  Te-Hsin Chiu ,  Wei-An Lai ,  Ching-Wei Tsai ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

公开(公告)号：US20240363396A1

公开(公告)日：2024-10-31

申请号：US18768125

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Yuan Chen ,  Pei-Yu Wang ,  Huan-Chieh Su ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/762 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/28017 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/785

Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.

公开(公告)号：US12034045B2

公开(公告)日：2024-07-09

申请号：US18171091

申请日：2023-02-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Ching-Wei Tsai

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/7845 ,  H01L29/78618

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The gate stack is partially embedded in the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer. A first portion of the contact structure is between the first source/drain layer and the substrate.

公开(公告)号：US11854940B2

公开(公告)日：2023-12-26

申请号：US17231527

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chih-Yu Lai ,  Chih-Liang Chen ,  Chi-Yu Lu ,  Shang-Syuan Ciou ,  Hui-Zhong Zhuang ,  Ching-Wei Tsai ,  Shang-Wen Chang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/76897 ,  H01L21/76898

Abstract: A semiconductor device includes a substrate and a first transistor on a first side of the substrate. The semiconductor device further includes a first electrode contacting a first region of the first transistor. The semiconductor device further includes a spacer extending along a sidewall of the first transistor. The semiconductor device further includes a self-aligned interconnect structure (SIS) separated from at least a portion of the first electrode by the spacer, wherein the SIS extends through the substrate. The semiconductor device further includes a second electrode contacting a surface of the first electrode farthest from the substrate, wherein the second electrode directly contacts the SIS.

公开(公告)号：US11824058B2

公开(公告)日：2023-11-21

申请号：US18082333

申请日：2022-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L27/0924 ,  H01L21/28088 ,  H01L21/3086 ,  H01L21/823821 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/785

Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The method for forming a semiconductor device includes forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device. The first stack of channel structures includes a first channel structure and a second channel structure. The method further includes forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.

公开(公告)号：US20230253483A1

公开(公告)日：2023-08-10

申请号：US18305086

申请日：2023-04-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L29/785 ,  H01L29/66545

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple first semiconductor nanostructures over a first semiconductor fin and multiple second semiconductor nanostructures over a second semiconductor fin. A topmost second semiconductor nanostructure of the second semiconductor nanostructures is thinner than one or more of lower semiconductor nanostructures of the second semiconductor nanostructures. The semiconductor device structure also includes a first metal gate stack wrapped around the first semiconductor nanostructures. The semiconductor device structure further includes a second metal gate stack wrapped around the second semiconductor nano structures.

公开(公告)号：US11640989B2

公开(公告)日：2023-05-02

申请号：US17665925

申请日：2022-02-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78

Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first structure and a second structure. The method further includes replacing the second structure with a third structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first structure and the second sacrificial layers in the third structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first structure and each of the second semiconductor layers in the third structure, respectively.

公开(公告)号：US11367659B2

公开(公告)日：2022-06-21

申请号：US16726518

申请日：2019-12-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Ying-Keung Leung

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/161 ,  H01L29/16 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

公开(公告)号：US11031298B2

公开(公告)日：2021-06-08

申请号：US16504786

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Bo Liao ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/092

Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

公开(公告)号：US11024650B2

公开(公告)日：2021-06-01

申请号：US16395494

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wang-Chun Huang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Chen ,  Chih-Hao Wang

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/06 ,  H01L29/26 ,  H01L29/24 ,  H01L29/16 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10 ,  H01L21/308

Abstract: A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.