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1.
公开(公告)号:US20240364341A1
公开(公告)日:2024-10-31
申请号:US18767158
申请日:2024-07-09
IPC分类号: H03K19/0185 , H03K3/037
CPC分类号: H03K19/018521 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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公开(公告)号:US11764784B2
公开(公告)日:2023-09-19
申请号:US17571690
申请日:2022-01-10
IPC分类号: H03K19/0185 , H03K3/037
CPC分类号: H03K19/018521 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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3.
公开(公告)号:US20230396252A1
公开(公告)日:2023-12-07
申请号:US18447369
申请日:2023-08-10
IPC分类号: H03K19/0185 , H03K3/037
CPC分类号: H03K19/018521 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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公开(公告)号:US20230008990A1
公开(公告)日:2023-01-12
申请号:US17571690
申请日:2022-01-10
IPC分类号: H03K19/0185 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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5.
公开(公告)号:US20230387914A1
公开(公告)日:2023-11-30
申请号:US18446849
申请日:2023-08-09
IPC分类号: H03K19/0185 , H03K3/037
CPC分类号: H03K19/018521 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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公开(公告)号:US20230230625A1
公开(公告)日:2023-07-20
申请号:US17749228
申请日:2022-05-20
发明人: Shiba Mohanty , Atul Katoch
摘要: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N-1 memory array at a time. A method of operating the semiconductor device is also disclosed.
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公开(公告)号:US20240331750A1
公开(公告)日:2024-10-03
申请号:US18739554
申请日:2024-06-11
发明人: Shiba Mohanty , Atul Katoch
摘要: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N−1 memory array at a time. A method of operating the semiconductor device is also disclosed.
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公开(公告)号:US12088295B2
公开(公告)日:2024-09-10
申请号:US18447369
申请日:2023-08-10
IPC分类号: H03K19/0185 , H03K3/037
CPC分类号: H03K19/018521 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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公开(公告)号:US12057832B2
公开(公告)日:2024-08-06
申请号:US18447372
申请日:2023-08-10
IPC分类号: H03K19/0185 , H03K3/037
CPC分类号: H03K19/018521 , H03K3/037
摘要: A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.
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公开(公告)号:US12033719B2
公开(公告)日:2024-07-09
申请号:US17749228
申请日:2022-05-20
发明人: Shiba Mohanty , Atul Katoch
摘要: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N−1 memory array at a time. A method of operating the semiconductor device is also disclosed.
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