Semiconductor Device and Method of Operating the Same

    公开(公告)号:US20230230625A1

    公开(公告)日:2023-07-20

    申请号:US17749228

    申请日:2022-05-20

    IPC分类号: G11C7/12 G11C7/14

    CPC分类号: G11C7/12 G11C7/14

    摘要: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N-1 memory array at a time. A method of operating the semiconductor device is also disclosed.

    Semiconductor Device and Method of Operating the Same

    公开(公告)号:US20240331750A1

    公开(公告)日:2024-10-03

    申请号:US18739554

    申请日:2024-06-11

    IPC分类号: G11C7/12 G11C7/14

    CPC分类号: G11C7/12 G11C7/14

    摘要: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N−1 memory array at a time. A method of operating the semiconductor device is also disclosed.

    Semiconductor device and method of operating the same

    公开(公告)号:US12033719B2

    公开(公告)日:2024-07-09

    申请号:US17749228

    申请日:2022-05-20

    IPC分类号: G11C7/12 G11C7/14

    CPC分类号: G11C7/12 G11C7/14

    摘要: A semiconductor device includes a memory bank. The memory bank includes a plurality N of memory arrays and a local control circuit. Each memory array includes a plurality of bit cells configured to store bits of information and connected between a plurality of bit lines and a plurality of complement bit lines. The local control circuit is configured to pre-charge the bit lines and the complement bit lines at most N−1 memory array at a time. A method of operating the semiconductor device is also disclosed.