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公开(公告)号：US20210151434A1
公开(公告)日：2021-05-20
申请号：US17140289
申请日：2021-01-04
发明人： Winnie Victoria Wei-Ning CHEN , Meng-Hsuan HSIAO , Tung-Ying LEE , Pang-Yen TSAI , Yasutoshi OKUNO
IPC分类号： H01L27/092 , H01L29/423 , H01L29/06 , H01L21/306 , H01L29/16 , H01L21/02 , H01L29/10 , H01L21/8238
摘要： A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.
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公开(公告)号：US20240186417A1
公开(公告)日：2024-06-06
申请号：US18442574
申请日：2024-02-15
发明人： Yu-Chao LIN , Wei-Sheng YUN , Tung-Ying LEE
CPC分类号： H01L29/7855 , H01L29/0649 , H01L29/0665 , H01L29/6681
摘要： A semiconductor device structure is provided. The semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate, and a first gate structure formed over the first nanostructures. The semiconductor device structure includes a second gate structure formed over the second nanostructures, and the second gate structure includes a gate dielectric layer, a first type work function layer and a filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and the first isolation layer includes a first sidewall surface, and the first sidewall surface is in direct contact with a first interface between the gate dielectric layer and the first type work function layer and a second interface between the work function layer and the filling layer.
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公开(公告)号：US20210134970A1
公开(公告)日：2021-05-06
申请号：US17028683
申请日：2020-09-22
发明人： Tung-Ying LEE , Kai-Tai CHANG
IPC分类号： H01L29/417 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/40 , H01L29/423
摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The method includes forming an isolation layer over the base. The method includes forming a gate dielectric layer over the first nanostructure, the second nanostructure, the fin, and the isolation layer. The method includes forming a gate electrode layer over the first part. The method includes forming a spacer layer. The method includes removing the second part of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and over the first nanostructure and the second nanostructure.
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公开(公告)号：US20240347635A1
公开(公告)日：2024-10-17
申请号：US18751953
申请日：2024-06-24
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/66
CPC分类号： H01L29/785 , H01L21/823431 , H01L29/0665 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. The dielectric structure covers a top surface, an inner wall, and a lower surface of the inner spacer layer.
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公开(公告)号：US20220352366A1
公开(公告)日：2022-11-03
申请号：US17866803
申请日：2022-07-18
IPC分类号： H01L29/78 , H01L29/06 , H01L29/66 , H01L21/8234 , H01L29/417
摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, a second nanostructure, a metal gate stack, and a spacer structure. The first nanostructure is between the second nanostructure and the substrate, the metal gate stack surrounds the first nanostructure and the second nanostructure, and the spacer structure surrounds an upper portion of the metal gate stack over the second nanostructure. The method includes removing the upper portion of the metal gate stack to form a first trench in the spacer structure. The method includes removing a first portion of the second nanostructure through the first trench after removing the upper portion of the metal gate stack.
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公开(公告)号：US20220328480A1
公开(公告)日：2022-10-13
申请号：US17846543
申请日：2022-06-22
发明人： Winnie Victoria Wei-Ning CHEN , Meng-Hsuan HSIAO , Tung-Ying LEE , Pang-Yen TSAI , Yasutoshi OKUNO
IPC分类号： H01L27/092 , H01L29/423 , H01L29/06 , H01L21/306 , H01L29/16 , H01L21/02 , H01L29/10 , H01L21/8238
摘要： A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.
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公开(公告)号：US20230231054A1
公开(公告)日：2023-07-20
申请号：US18190625
申请日：2023-03-27
发明人： Yu-Chao LIN , Wei-Sheng YUN , Tung-Ying LEE
CPC分类号： H01L29/7855 , H01L29/6681 , H01L29/0649 , H01L29/0665
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, wherein the first isolation layer has an extending portion which is formed in a recess between the gate dielectric layer and the filling layer.
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公开(公告)号：US20220359506A1
公开(公告)日：2022-11-10
申请号：US17870133
申请日：2022-07-21
发明人： Jin-Aun NG , Yu-Chao LIN , Tung-Ying LEE
IPC分类号： H01L27/088 , H01L29/423 , H01L29/06 , H01L21/8234 , H01L29/66 , H01L21/762 , H01L21/306
摘要： A semiconductor structure is provided. The semiconductor structure includes a first gate-all-around FET over a substrate, and the first gate-all-around FET includes first nanostructures and a first gate stack surrounding the first nanostructures. The semiconductor structure also includes a first FinFET adjacent to the first gate-all-around FET, and the first FinFET includes a first fin structure and a second gate stack over the first fin structure. The semiconductor structure also includes a gate-cut feature interposing the first gate stack of the first gate-all-around FET and the second gate stack of the first FinFET.
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公开(公告)号：US20220254929A1
公开(公告)日：2022-08-11
申请号：US17729333
申请日：2022-04-26
发明人： Yu-Chao LIN , Wei-Sheng YUN , Tung-Ying LEE
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first stacked nanostructure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure includes a second gate structure formed over the second stacked nanostructure, and the second gate structure includes a second portion of the gate dielectric layer and a second portion of the filling layer. The semiconductor device structure includes a first isolation layer between the first gate structure and the second gate structure, and a sidewall of the first portion of the gate dielectric layer extends beyond a sidewall of the filling layer.
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