公开(公告)号：US20200212217A1

公开(公告)日：2020-07-02

申请号：US16726405

申请日：2019-12-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Ming YU ,  Chang-Yun CHANG ,  Chih-Hao CHANG ,  Hsin-Chih CHEN ,  Kai-Tai CHANG ,  Ming-Feng SHIEH ,  Kuei-Liang LU ,  Yi-Tang LIN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67 ,  H01L27/088

摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US20170271503A1

公开(公告)日：2017-09-21

申请号：US15614439

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Ming YU ,  Chang-Yun CHANG ,  Chih-Hao CHANG ,  Hsin-Chih CHEN ,  Kai-Tai CHANG ,  Ming-Feng SHIEH ,  Kuei-Liang LU ,  Yi-Tang LIN

IPC分类号： H01L29/78 ,  H01L29/66

摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US20220367678A1

公开(公告)日：2022-11-17

申请号：US17875144

申请日：2022-07-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Kai-Tai CHANG ,  Tung Ying LEE ,  Wei-Sheng YUN ,  Tzu-Chung WANG ,  Chia-Cheng HO ,  Ming-Shiang LIN ,  Tzu-Chiang CHEN

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L27/088

摘要： A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

公开(公告)号：US20220223727A1

公开(公告)日：2022-07-14

申请号：US17649148

申请日：2022-01-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Ming YU ,  Chang-Yun CHANG ,  Chih-Hao CHANG ,  Hsin-Chih CHEN ,  Kai-Tai CHANG ,  Ming-Feng SHIEH ,  Kuei-Liang LU ,  Yi-Tang LIN

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67 ,  H01L27/088

摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US20210134970A1

公开(公告)日：2021-05-06

申请号：US17028683

申请日：2020-09-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung-Ying LEE ,  Kai-Tai CHANG

IPC分类号： H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The method includes forming an isolation layer over the base. The method includes forming a gate dielectric layer over the first nanostructure, the second nanostructure, the fin, and the isolation layer. The method includes forming a gate electrode layer over the first part. The method includes forming a spacer layer. The method includes removing the second part of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and over the first nanostructure and the second nanostructure.