公开(公告)号：US20220359746A1

公开(公告)日：2022-11-10

申请号：US17874281

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yan-Ting SHEN ,  Chia-Chi YU ,  Chih-Teng LIAO ,  Yu-Li LIN ,  Chih Hsuan CHENG ,  Tzu-Chan WENG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US20240274668A1

公开(公告)日：2024-08-15

申请号：US18645481

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui Fu HSIEH ,  Chih-Teng LIAO ,  Chih-Shan CHEN ,  Yi-Jen CHEN ,  Tzu-Chan WENG

IPC: H01L29/08 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/32136 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US20240297253A1

公开(公告)日：2024-09-05

申请号：US18656852

申请日：2024-05-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yan-Ting SHEN ,  Chia-Chi YU ,  Chih-Teng LIAO ,  Yu-Li LIN ,  Chih Hsuan CHENG ,  Tzu-Chan WENG

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.