公开(公告)号：US20230036955A1

公开(公告)日：2023-02-02

申请号：US17388875

申请日：2021-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Lun KE ,  Yu-Chi LIN ,  Yi-Tsang HSIEH ,  Yu-Hsi TANG ,  Chih-Teng LIAO

IPC: H01J37/32 ,  H01L21/311

Abstract: A method for manufacturing a semiconductor structure includes disposing a wafer in a processing chamber, in which the wafer is laterally surrounded by a focus ring. A plasma is formed in the processing chamber to process the wafer. A thickness of the focus ring is detected. A plasma direction of the plasma over a peripheral region of the wafer is adjusted according to the thickness of the focus ring.

公开(公告)号：US20230024640A1

公开(公告)日：2023-01-26

申请号：US17377634

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Jui HE ,  Chih-Teng LIAO

IPC: H01L21/3213 ,  G06F30/39 ,  G03F1/70

Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

公开(公告)号：US20220130706A1

公开(公告)日：2022-04-28

申请号：US17572351

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Chi LIN ,  Huai-Tei YANG ,  Lun-Kuang TAN ,  Wei-Jen LO ,  Chih-Teng LIAO

IPC: H01L21/683 ,  H01L21/3065 ,  H01J37/32

Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.

公开(公告)号：US20220115370A1

公开(公告)日：2022-04-14

申请号：US17069365

申请日：2020-10-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Hung TSAI ,  Xi-Zong CHEN ,  Hsiao Chien LIN ,  Chia-Tsung TSO ,  Chih-Teng LIAO

IPC: H01L27/06 ,  H01L49/02

Abstract: A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.

公开(公告)号：US20240274668A1

公开(公告)日：2024-08-15

申请号：US18645481

申请日：2024-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui Fu HSIEH ,  Chih-Teng LIAO ,  Chih-Shan CHEN ,  Yi-Jen CHEN ,  Tzu-Chan WENG

IPC: H01L29/08 ,  H01L21/3213 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/32136 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

公开(公告)号：US20240203885A1

公开(公告)日：2024-06-20

申请号：US18590215

申请日：2024-02-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan LIN ,  Hsi Chung CHEN ,  Ji-Ling WU ,  Chih-Teng LIAO

IPC: H01L23/535 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/32136 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76825 ,  H01L21/76895 ,  H01L23/5283 ,  H01L23/53257

Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.

公开(公告)号：US20230386857A1

公开(公告)日：2023-11-30

申请号：US18447810

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yun-Jui HE ,  Chih-Teng LIAO

IPC: H01L21/3213 ,  G03F1/70 ,  G06F30/39

CPC classification number: H01L21/32137 ,  G03F1/70 ,  G06F30/39 ,  H01L21/32139

Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.

公开(公告)号：US20230378327A1

公开(公告)日：2023-11-23

申请号：US18231433

申请日：2023-08-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chen-Wei PAN ,  Jen-Chih HSUEH ,  Li-Feng CHU ,  Chih-Teng LIAO

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/66795 ,  H01L29/41791 ,  H01L29/7851 ,  H01L21/31116 ,  H01L21/823481 ,  H01L21/823468 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/42376 ,  H01L29/785

Abstract: In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

公开(公告)号：US20220384426A1

公开(公告)日：2022-12-01

申请号：US17819245

申请日：2022-08-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Cheng-Hung TSAI ,  Xi-Zong CHEN ,  Hsiao Chien LIN ,  Chia-Tsung TSO ,  Chih-Teng LIAO

IPC: H01L27/06 ,  H01L49/02

Abstract: A semiconductor device having source and drain regions in a semiconductor substrate, a transistor including a gate electrode over the semiconductor substrate, an isolation structure in the semiconductor substrate adjacent to the transistor, a first inter-dielectric layer (ILD) material over the isolation structure, and a capacitor film stack over the first ILD material that includes an isolation plate over and covering a capacitor plate, and a contact to the capacitor plate.

公开(公告)号：US20220328342A1

公开(公告)日：2022-10-13

申请号：US17225661

申请日：2021-04-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Huang-Shao KO ,  Jui-Fu HSIEH ,  Chih-Teng LIAO ,  Chih-Ching CHENG

IPC: H01L21/687 ,  H01L21/67 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/66 ,  H01J37/32

Abstract: A method for processing a semiconductor wafer is provided. The method includes placing a first semiconductor wafer on a wafer chuck in a process chamber. The method further includes adjusting a distance between a gas dispenser positioned above the wafer chuck and an upper edge ring surrounding the wafer chuck. The method also includes producing a plasma for processing the first semiconductor wafer by exciting a gas dispenser from the gas dispenser after the adjustment. In addition, the method includes removing the first semiconductor wafer from the process chamber.