公开(公告)号：US20160035629A1

公开(公告)日：2016-02-04

申请号：US14883935

申请日：2015-10-15

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHUN-WEN NIEH ,  HUNG-CHANG HSU ,  WEI-JUNG LIN ,  YAN-MING TSAI ,  CHEN-MING LEE ,  MEI-YUN WANG

IPC分类号： H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

摘要： Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.

公开(公告)号：US20150243565A1

公开(公告)日：2015-08-27

申请号：US14190226

申请日：2014-02-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHUN-WEN NIEH ,  HUNG-CHANG HSU ,  WEI-JUNG LIN ,  YAN-MING TSAI ,  CHEN-MING LEE ,  MEI-YUN WANG

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/45 ,  H01L21/283

CPC分类号： H01L21/823871 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

摘要： Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.

摘要翻译： 提供了形成电触点的方法。 第一和第二FET形成在半导体衬底上。 在形成在衬底上的电介质层中蚀刻开口，其中开口延伸到FET的源极和漏极区域。 在FET的源极和漏极区域上形成硬掩模。 去除硬掩模的第一部分，其中第一部分形成在第一FET的源极和漏极区域上。 在第一FET的源极和漏极区域上形成第一硅化物层。 去除硬掩模的第二部分，其中第二部分形成在第二FET的源极和漏极区域上。 在第二FET的源极和漏极区域上形成第二硅化物层。 在开口内沉积金属层以填充开口。