公开(公告)号：US20150170964A1

公开(公告)日：2015-06-18

申请号：US14108819

申请日：2013-12-17

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHI-YUAN CHEN ,  LI-TING WANG ,  TENG-CHUN TSAI ,  CHUN-I TSAI ,  WEI-JUNG LIN ,  HUANG-YI HUANG ,  CHENG-TUNG LIN ,  HONG-MAO LEE

IPC分类号： H01L21/768 ,  C23C14/58 ,  C23C14/48

CPC分类号： H01L21/02694 ,  C23C14/046 ,  C23C14/48 ,  C23C14/5873 ,  H01L21/02697 ,  H01L21/0415 ,  H01L21/046 ,  H01L21/2253 ,  H01L21/31155 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/3215 ,  H01L21/76224 ,  H01L21/76254 ,  H01L21/76859 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L29/66734 ,  H01L2224/05157 ,  H01L2924/01002 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01022 ,  H01L2924/01074

摘要： Systems and methods are provided for contact formation. A semiconductor structure is provided. The semiconductor structure includes an opening formed by a bottom surface and one or more side surfaces. A first conductive material is formed on the bottom surface and the one or more side surfaces to partially fill the opening, the first conductive material including a top portion and a bottom portion. Ion implantation is formed on the first conductive material, the top portion of the first conductive material being associated with a first ion density, the bottom portion of the first conductive material being associated with a second ion density lower than the first ion density. At least part of the top portion of the first conductive material is removed. A second conductive material is formed to fill the opening.

摘要翻译： 为接触形成提供了系统和方法。 提供半导体结构。 半导体结构包括由底表面和一个或多个侧表面形成的开口。 第一导电材料形成在底表面和一个或多个侧表面上以部分地填充开口，第一导电材料包括顶部和底部。 在第一导电材料上形成离子注入，第一导电材料的顶部与第一离子密度相关联，第一导电材料的底部与低于第一离子密度的第二离子密度相关联。 去除第一导电材料的顶部的至少一部分。 形成第二导电材料以填充开口。

公开(公告)号：US20160035629A1

公开(公告)日：2016-02-04

申请号：US14883935

申请日：2015-10-15

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHUN-WEN NIEH ,  HUNG-CHANG HSU ,  WEI-JUNG LIN ,  YAN-MING TSAI ,  CHEN-MING LEE ,  MEI-YUN WANG

IPC分类号： H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

摘要： Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.

公开(公告)号：US20150243565A1

公开(公告)日：2015-08-27

申请号：US14190226

申请日：2014-02-26

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHUN-WEN NIEH ,  HUNG-CHANG HSU ,  WEI-JUNG LIN ,  YAN-MING TSAI ,  CHEN-MING LEE ,  MEI-YUN WANG

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/45 ,  H01L21/283

CPC分类号： H01L21/823871 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665

摘要： Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.

摘要翻译： 提供了形成电触点的方法。 第一和第二FET形成在半导体衬底上。 在形成在衬底上的电介质层中蚀刻开口，其中开口延伸到FET的源极和漏极区域。 在FET的源极和漏极区域上形成硬掩模。 去除硬掩模的第一部分，其中第一部分形成在第一FET的源极和漏极区域上。 在第一FET的源极和漏极区域上形成第一硅化物层。 去除硬掩模的第二部分，其中第二部分形成在第二FET的源极和漏极区域上。 在第二FET的源极和漏极区域上形成第二硅化物层。 在开口内沉积金属层以填充开口。

公开(公告)号：US20150021757A1

公开(公告)日：2015-01-22

申请号：US13945422

申请日：2013-07-18

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： CHENG-TUNG LIN ,  TENG-CHUN TSAI ,  LI-TING WANG ,  CHI-YUAN CHEN ,  HONG-MAO LEE ,  HUI-CHENG CHANG ,  WEI-JUNG LIN ,  BING-HUNG CHEN ,  CHIA-HAN LAI

IPC分类号： H01L23/48 ,  H01L21/02

CPC分类号： H01L21/76831 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/28512 ,  H01L21/28575 ,  H01L21/3105 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/823418 ,  H01L21/823437 ,  H01L29/45 ,  H01L29/452 ,  H01L29/456 ,  H01L2924/0002 ,  H01L2924/00

摘要： Systems and methods are provided for reducing a contact resistivity associated with a semiconductor device structure. A substrate including a semiconductor region is provided. One or more dielectric layers are formed on the semiconductor region, the one or more dielectric layers including an element. A gaseous material is applied on the one or more dielectric layers to change a concentration of the element in the one or more dielectric layers. A contact layer is formed on the one or more dielectric layers to generate a semiconductor device structure. The semiconductor device structure includes the contact layer, the one or more dielectric layers, and the semiconductor region. A contact resistivity associated with the semiconductor device structure is reduced by changing the concentration of the element in the one or more dielectric layers.

摘要翻译： 提供了用于降低与半导体器件结构相关联的接触电阻的系统和方法。 提供了包括半导体区域的衬底。 在半导体区域上形成一个或多个电介质层，所述一个或多个电介质层包括元件。 在一个或多个电介质层上施加气态材料以改变一个或多个电介质层中的元素的浓度。 在一个或多个电介质层上形成接触层以产生半导体器件结构。 半导体器件结构包括接触层，一个或多个电介质层和半导体区域。 通过改变一个或多个电介质层中的元素的浓度来减少与半导体器件结构相关联的接触电阻。