公开(公告)号：US11894425B2

公开(公告)日：2024-02-06

申请号：US18106001

申请日：2023-02-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yun-Chi Wu ,  Tsung-Yu Yang ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC分类号： H01L29/08 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H10B10/00

CPC分类号： H01L29/0847 ,  H01L21/0276 ,  H01L21/02164 ,  H01L21/266 ,  H01L21/2652 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/401 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66545 ,  H01L29/7833 ,  H10B10/12

摘要： A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

公开(公告)号：US11575008B2

公开(公告)日：2023-02-07

申请号：US17098751

申请日：2020-11-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Yun-Chi Wu ,  Tsung-Yu Yang ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC分类号： H01L29/08 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L27/11

摘要： A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

公开(公告)号：US20210066456A1

公开(公告)日：2021-03-04

申请号：US17098751

申请日：2020-11-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Yun-Chi WU ,  Tsung-Yu Yang ,  Cheng-Bo Shu ,  Chien Hung Liu

IPC分类号： H01L29/08 ,  H01L29/40 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L29/66 ,  H01L21/027 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02

摘要： A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.