公开(公告)号：US20080294878A1

公开(公告)日：2008-11-27

申请号：US12101437

申请日：2008-04-11

申请人： Takafumi YUASA ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Fumitaka Izuhara ,  Kazushi Akie

发明人： Takafumi YUASA ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Fumitaka Izuhara ,  Kazushi Akie

IPC分类号： G06F9/38 ,  G06F9/302 ,  G06F9/312

CPC分类号： G06F11/0793 ,  G06F9/30054 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4812 ,  G06F11/0721 ,  G06F2209/481

摘要： When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.

摘要翻译： 当在处理器系统中的错误检测单元中检测到错误时，错误检测单元向中断控制单元输出错误信号，并且中断控制单元向程序计数器输出错误地址寄存器和控制信号的值 控制单元，并将程序计数器的值重写为错误地址寄存器的值。 通过这种方式，实现了通过错误中断的分支过程。 在这种情况下，当检测到错误时，不执行在发生错误时保存程序计数器的值的处理，以及特定的存储寄存器和控制电路，用于恢复到发生错误时的地址 未提供错误处理结束后的错误发生。

公开(公告)号：US20110080308A1

公开(公告)日：2011-04-07

申请号：US12961017

申请日：2010-12-06

申请人： Hiroaki NAKATA ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

发明人： Hiroaki NAKATA ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46 ,  H04N19/115 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.

摘要翻译： 一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其根据解码数据依次选择解码处理表以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表来执行可变长度代码数据的初始解码时， 当参考解码处理表的其他部分时，使用比用于参考解码处理表的可变长度代码数据更长的比特长进行初始解码处理。

公开(公告)号：US07864082B2

公开(公告)日：2011-01-04

申请号：US12467556

申请日：2009-05-18

申请人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

发明人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46 ,  H04N19/115 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that is given a start address and an initial reference bit length of the table memory; and sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.

摘要翻译： 一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其被给予所述表存储器的起始地址和初始参考位长度; 并根据解码数据依次选择解码处理表，以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表执行可变长度代码数据的初始解码时，进行初始解码处理 通过比参考解码处理表的其他部分使用的比特长度从参考解码处理表的可变长度代码数据中减去更长的比特长度。

公开(公告)号：US20080212683A1

公开(公告)日：2008-09-04

申请号：US11939807

申请日：2007-11-14

申请人： Hiroaki Nakata ,  Takafumi Yuasa ,  Fumitaka Izuhara ,  Kazushi Akie

发明人： Hiroaki Nakata ,  Takafumi Yuasa ,  Fumitaka Izuhara ,  Kazushi Akie

IPC分类号： G06K9/36

CPC分类号： H04N19/436 ,  H04N19/12 ,  H04N19/13 ,  H04N19/44 ,  H04N19/70

摘要： An image decoding device according to the present invention is an image decoding device responding to decoding of an image encoding method selecting an encoding table and an encoding format to use according to the kind of a parameter included in encoded data and comprises a bit stream processing unit converting a bit stream of the encoded data into an intermediate format and an image processing unit decoding data converted into the intermediate format and converting the same into image data. The bit stream processing unit and the image processing unit start independently. An image encoding device according to the present invention, in the same manner, comprises an image processing unit converting image data to be encoded into an intermediate format and a bit stream processing unit encoding the data converted into the intermediate format and converting the same into a bit stream. Thereby, image encoding and decoding processings with a low operation frequency and low power consumption is realized.

摘要翻译： 根据本发明的图像解码装置是响应于根据编码数据中包括的参数的种类选择编码表和编码格式的图像编码方法的解码的图像解码装置，并且包括位流处理单元 将编码数据的比特流转换为中间格式，以及图像处理单元，将转换成中间格式的数据解码并转换为图像数据。 位流处理单元和图像处理单元独立地起动。 根据本发明的图像编码装置以相同的方式，包括将要编码的图像数据转换为中间格式的图像处理单元和将转换成中间格式的数据编码为比特流处理单元，并将其转换为 位流。 从而，实现了低操作频率和低功耗的图像编码和解码处理。

公开(公告)号：US20080068235A1

公开(公告)日：2008-03-20

申请号：US11845850

申请日：2007-08-28

申请人： HIROAKI NAKATA ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

发明人： HIROAKI NAKATA ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

IPC分类号： H03M7/42

CPC分类号： H03M7/425 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46 ,  H04N19/115 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

摘要： A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.

摘要翻译： 指示解码处理是否完成或继续的标志被布置在解码处理表的每个条目中。 在解码处理完成的条目中记录解码值和有效位长度。 用于识别在后续处理中使用的解码处理表的信息和从参考后续表时使用的代码字剪切的位长度被记录在解码处理继续的条目中。 当解码处理开始时，与代码字一起指定用于识别要使用的表的信息和当参考表时从代码字引用的位长度。 根据需要重复解码过程表参考。 通过上述结构，提供了可变长度码解码装置。

公开(公告)号：US08884792B2

公开(公告)日：2014-11-11

申请号：US13602360

申请日：2012-09-04

申请人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

发明人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

IPC分类号： H03M7/40 ,  H03M7/42 ,  H04N19/176 ,  H03M7/30 ,  H04N19/61 ,  H03M7/46

CPC分类号： H03M7/425 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46 ,  H04N19/115 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

摘要： Variable length code decoding device for decoding variable length code data, including: decoding process tables each including at least two kinds of formats consisting a first format storing identification information for designating a subsequent table to be referred to in a subsequent decoding process, and a second format that stores a decoded value obtained by repeating the decoding process and a significant bit length to be referred to with respect to variable length code data. The device utilizes first, second, third and fourth formats and relative addresses.

摘要翻译： 可变长度码解码装置，用于解码可变长度码数据，包括：解码处理表，每个包括至少两种格式，包括第一格式，第一格式存储用于指定随后的解码过程中要参考的后续表的标识信息;以及第二 格式，其存储通过重复解码处理而获得的解码值以及关于可变长度代码数据参考的有效位长度。 该设备利用第一，第二，第三和第四格式和相对地址。

公开(公告)号：US08264386B2

公开(公告)日：2012-09-11

申请号：US12961017

申请日：2010-12-06

申请人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

发明人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46 ,  H04N19/115 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

摘要： A variable length code decoding device for decoding variable length code data, including: a table memory that stores a plurality of decoding process tables having a reference relationship therein; and a decoding control unit that sequentially selects the decoding process tables according to the decoded data to control a process of decoding the variable length code data, wherein when referring to the decoding process table to perform an initial decoding of the variable length code data, the initial decoding process is conducted by a longer bit length to be clipped from the variable length code data for referring to the decoding process table than the bit length used when referring to the other portions of the decoding process table.

摘要翻译： 一种用于解码可变长度码数据的可变长度码解码装置，包括：存储多个具有参考关系的解码处理表的表存储器; 以及解码控制单元，其根据解码数据依次选择解码处理表以控制对可变长度代码数据进行解码的处理，其中当参考解码处理表来执行可变长度代码数据的初始解码时， 当参考解码处理表的其他部分时，使用比用于参考解码处理表的可变长度代码数据更长的比特长进行初始解码处理。

公开(公告)号：US07535386B2

公开(公告)日：2009-05-19

申请号：US11845850

申请日：2007-08-28

申请人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

发明人： Hiroaki Nakata ,  Fumitaka Izuhara ,  Kazushi Akie ,  Takafumi Yuasa

IPC分类号： H03M7/40

CPC分类号： H03M7/425 ,  H03M7/30 ,  H03M7/40 ,  H03M7/46 ,  H04N19/115 ,  H04N19/12 ,  H04N19/176 ,  H04N19/61

摘要： A flag indicating whether a decoding process is completed or continued is disposed in each of entries of a decoding process table. A decoded value and a significant bit length are recorded in the entry of a decoding process completion. Information for identifying the decoding process table which is used in a subsequent process, and a bit length that is clipped from a code word which is used when referring to a subsequent table are recorded in the entry of the decoding process continuation. When the decoding process starts, the information for identifying the table to be used and the bit length that is referred to from the code word when referring to the table are designated together with the code word. The decoding process table reference is repeated as the occasion demands. With the above configuration, there is provided a variable length code decoding device.

摘要翻译： 指示解码处理是否完成或继续的标志被布置在解码处理表的每个条目中。 在解码处理完成的条目中记录解码值和有效位长度。 用于识别在后续处理中使用的解码处理表的信息和从参考后续表时使用的代码字剪切的位长度被记录在解码处理继续的条目中。 当解码处理开始时，与代码字一起指定用于识别要使用的表的信息和当参考表时从代码字引用的位长度。 根据需要重复解码过程表参考。 通过上述结构，提供了可变长度码解码装置。

公开(公告)号：US20110238964A1

公开(公告)日：2011-09-29

申请号：US13073992

申请日：2011-03-28

申请人： Takafumi YUASA ,  Hiroaki Nakata ,  Motoki Kimura ,  Kazushi Akie

发明人： Takafumi YUASA ,  Hiroaki Nakata ,  Motoki Kimura ,  Kazushi Akie

IPC分类号： G06F9/38

CPC分类号： G06F9/30101 ,  G06F9/30058 ,  G06F9/30192 ,  G06F9/322

摘要： The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.

摘要翻译： 数据处理器包括可操作以执行包括在指令集中的指令的CPU。 指令集包括用于读取存储器空间上的数据的加载指令。 根据加载指令读取的数据包括具有数据读取分支出现位区域的格式类型的数据。 CPU包括数据读取分支控制寄存器; 数据读取分支地址寄存器; 和读数据分析单元。 在数据读取分支发生位区域上设置了表示数据读取分支出现的位值的条件下，在数据读取分支发生位区域上设定了表示数据读取分支发生位保持有效的值， 读分支控制寄存器，通过分支到存储在数据读分支地址寄存器中的地址来执行处理之间的切换。

公开(公告)号：US09619228B2

公开(公告)日：2017-04-11

申请号：US13073992

申请日：2011-03-28

申请人： Takafumi Yuasa ,  Hiroaki Nakata ,  Motoki Kimura ,  Kazushi Akie

发明人： Takafumi Yuasa ,  Hiroaki Nakata ,  Motoki Kimura ,  Kazushi Akie

IPC分类号： G06F9/30 ,  G06F9/32

CPC分类号： G06F9/30101 ,  G06F9/30058 ,  G06F9/30192 ,  G06F9/322

摘要： The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.