公开(公告)号：US08823691B2

公开(公告)日：2014-09-02

申请号：US13348673

申请日：2012-01-12

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0281 ,  G09G2320/0219

摘要： A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.

摘要翻译： 显示装置包括：多个像素组，每个像素组包括像素电路; 多个扫描线，其各自连接到包括在任何一个像素组中的像素电路; 时钟信号供给电路，其提供包括脉冲信号的时钟信号; 移位寄存器电路，其以预定顺序选择性地将扫描线传送到扫描线; 以及连接到像素电路并且将数据信号提供给要扫描的像素组中包括的像素电路的数据信号线。 提供给一些扫描线的脉冲信号的周期长于提供给其它扫描线的脉冲信号的周期，或者数据信号由包括在像素电路中的晶体管传输。

公开(公告)号：US09336899B2

公开(公告)日：2016-05-10

申请号：US13334280

申请日：2011-12-22

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G09G3/34 ,  G11C19/28 ,  G09G3/36

CPC分类号： G11C19/287 ,  G09G3/3677 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021

摘要： A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.

摘要翻译： 提供能够在两个方向上执行稳定的移位操作的双向移位寄存器和使用其的图像显示装置。 在正向移位操作中，当参考点N1处于H电平时，作为双向移位寄存器的后级的第（n + 4）单位寄存器电路与时钟脉冲V（n + 4）同步地输出脉冲G（n + 4）输入到第（n + 4）个单元寄存器电路。 不仅在反向开始时产生反向触发信号VSTB，而且例如在紧接在G（n + 4）之后的单相时钟的周期（时刻t4〜t5）中垂直输出 向前移位的消隐间隔。 反向触发信号VSTB被输入到在第（n + 4）个单位寄存器电路的参考点N1设置为H电平的晶体管的栅极上，在反向启动时为止。

公开(公告)号：US08912992B2

公开(公告)日：2014-12-16

申请号：US13437038

申请日：2012-04-02

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Motoharu Miyamoto

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Motoharu Miyamoto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2310/0205 ,  G09G2310/08

摘要： A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.

摘要翻译： 显示装置包括：驱动电路，其施加作为使像素晶体管顺序地接通到多个输出信号线的电位的有效电位，其中，所述驱动电路包括将所述有源电位输出到所述输出的一端的主驱动电路 通过施加由从上部输出信号线输出的有效电位的输入引起的时钟信号，以及具有作为晶体管的辅助晶体管的辅助晶体管的多个输出信号线的信号线， 输出信号线通过源极或漏极连接到时钟信号的信号线。 由此，能够提高扫描信号线的输出波形失真，能够提高显示质量。

公开(公告)号：US20120075282A1

公开(公告)日：2012-03-29

申请号：US13239789

申请日：2011-09-22

申请人： Hiroyuki HIGASHIJIMA ,  Takahiro Ochiai ,  Mitsuru Goto

发明人： Hiroyuki HIGASHIJIMA ,  Takahiro Ochiai ,  Mitsuru Goto

IPC分类号： G09G5/00

CPC分类号： G09G3/3677

摘要： In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors T6A, T6B are connected between the output terminal OUT and AC power sources VA, VB. At least one of T6A, T6B is brought into ON state and T6A, T6B are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where T6A, T6B are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where T6A, T6B are in OFF state.

摘要翻译： 在移位寄存器的各级的单位驱动电路中，在阶段的单位驱动电路不执行输出动作的期间内保持导通状态的晶体管被​​构成为不产生Vth偏移。 作为开关，晶体管T6A，T6B连接在输出端子OUT和AC电源VA，VB之间。 T6A，T6B中的至少一个变为导通状态，并且在输出操作期间以外的期间，T6A，T6B交替进入截止状态。 VA，VB在T6A，T6B处于导通状态的期间供给L电平，而在V6B，T6B为OFF的期间，VA，VB提供作为H电平和L电平之间的中间电位的地电位GND 州。

公开(公告)号：US08803783B2

公开(公告)日：2014-08-12

申请号：US13164833

申请日：2011-06-21

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroko Sehata ,  Hiroyuki Higashijima

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroko Sehata ,  Hiroyuki Higashijima

IPC分类号： G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0413 ,  G09G2300/0465 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2310/08

摘要： A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk−1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk−2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.

摘要翻译： 包括双向移位寄存器的多个级联单元寄存器电路包括在主级之前的顶级的主级和虚级，以及在主级后的底部的虚级。 第k级与参考点N1处于H电平的时钟信号同步地输出脉冲Pk。 主要分别包括用于设置输入Pk-1和Pk + 1的N1到H的端子NSF和NSB，以及用于设置输入Pk-2和Pk + 2的N1到L电平的端子NRB和NRF， 分别。 时钟信号的产生顺序根据移位方向反转，开始触发信号是施加到上一级还是下级切换。 顶级虚拟阶段没有NRB。 底部虚拟阶段没有NRF。

公开(公告)号：US20120262441A1

公开(公告)日：2012-10-18

申请号：US13437038

申请日：2012-04-02

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Motoharu Miyamoto

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Motoharu Miyamoto

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2310/0205 ,  G09G2310/08

摘要： A display device includes a driving circuit that applies an active potential which is a potential for turning on pixel transistors sequentially to a plurality of output signal lines, wherein the driving circuit includes a main driving circuit that outputs the active potential to one end of the output signal line of the plurality of output signal lines by applying a clock signal caused by a input of the active potential output from the upper output signal line, and an auxiliary driving circuit that has an auxiliary transistor which is a transistor where the other end of the output signal line is connected to a signal line for the clock signal via the source or the drain. Thereby, output waveform distortion in the scanning signal line can be improved and thus display quality can be enhanced.

摘要翻译： 显示装置包括：驱动电路，其施加作为使像素晶体管顺序地接通到多个输出信号线的电位的有效电位，其中，所述驱动电路包括将所述有源电位输出到所述输出的一端的主驱动电路 通过施加由从上部输出信号线输出的有效电位的输入引起的时钟信号，以及具有作为晶体管的辅助晶体管的辅助晶体管的多个输出信号线的信号线， 输出信号线通过源极或漏极连接到时钟信号的信号线。 由此，能够提高扫描信号线的输出波形失真，能够提高显示质量。

公开(公告)号：US08933870B2

公开(公告)日：2015-01-13

申请号：US13239789

申请日：2011-09-22

申请人： Hiroyuki Higashijima ,  Takahiro Ochiai ,  Mitsuru Goto

发明人： Hiroyuki Higashijima ,  Takahiro Ochiai ,  Mitsuru Goto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677

摘要： In a unit drive circuit in each stage in a shift register, a transistor which is maintained in ON state during a period where the unit drive circuit in the stage does not perform an outputting operation is configured not to generate Vth shift. As switches, transistors T6A, T6B are connected between the output terminal OUT and AC power sources VA, VB. At least one of T6A, T6B is brought into ON state and T6A, T6B are alternately brought into OFF state during the period other than the outputting operation period. VA, VB supply L level during a period where T6A, T6B are in ON state, while VA, VB supply a ground potential GND which is an intermediate potential between an H level and an L level during a period where T6A, T6B are in OFF state.

摘要翻译： 在移位寄存器的各级的单位驱动电路中，在阶段的单位驱动电路不执行输出动作的期间内保持导通状态的晶体管被​​构成为不产生Vth偏移。 作为开关，晶体管T6A，T6B连接在输出端子OUT和AC电源VA，VB之间。 T6A，T6B中的至少一个变为导通状态，并且在输出操作期间以外的期间，T6A，T6B交替进入截止状态。 VA，VB在T6A，T6B处于导通状态的期间供给L电平，而在V6B，T6B为OFF的期间，VA，VB提供作为H电平和L电平之间的中间电位的地电位GND 州。

公开(公告)号：US08803782B2

公开(公告)日：2014-08-12

申请号：US13164811

申请日：2011-06-21

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroko Sehata ,  Hiroyuki Higashijima

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroko Sehata ,  Hiroyuki Higashijima

IPC分类号： G09G3/34

CPC分类号： G09G3/3648 ,  G09G3/3674 ,  G09G2310/0286 ,  G09G2310/066 ,  G09G2330/025 ,  G11C19/184 ,  G11C19/28

摘要： A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A λth stage of unit register circuit (38) has two set terminals connected to respective outputs of (λ−1)th and (λ+1)th stages and two reset terminals connected to respective outputs of (λ+2)th and (λ−2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.

摘要翻译： 双向移位寄存器以多个级联单元寄存器电路以正向和反向之一的移位顺序输出脉冲。 单元寄存器电路（38）的第λ级具有连接到（λ-1）和（λ+ 1）级的相应输出的两个设定端子和连接到（λ+ 2）的各个输出的两个复位端子和（ λ-2）级。 当单位寄存器电路（38）将脉冲输入到设定端子中的任何一个时，将参考点N1设置为H电平，并且当将脉冲输入到复位端子中的任何一个N1至L 水平。 时钟信号的相位变化顺序根据移位方向反转，开始触发信号是施加到顶级还是下级切换。

公开(公告)号：US08542179B2

公开(公告)日：2013-09-24

申请号：US12977941

申请日：2010-12-23

申请人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

发明人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

摘要： A gate signal line driving circuit and a display device includes first and second low voltage application switching elements that supply a low voltage to gate signal lines, a holding capacitor that is connected to a reset target node and supplies an ON signal towards the first and second low voltage application switching elements in a signal low period, first and third control switching elements the one ends of which are connected to the switch input of the first or second low voltage application switching element, and second and fourth control switching elements which each are provided between the switch input of the first or second low voltage application switching element and one end of the holding capacitor. In a startup period, a high voltage is supplied to the holding capacitor through the first to fourth control switching elements.

摘要翻译： 栅极信号线驱动电路和显示装置包括向栅极信号线提供低电压的第一和第二低电压施加开关元件，连接到复位目标节点的保持电容器，并向第一和第二 信号低周期中的低电压应用开关元件，其一端连接到第一或第二低电压应用开关元件的开关输入的第一和第三控制开关元件，以及各自提供的第二和第四控制开关元件 在第一或第二低电压施加开关元件的开关输入和保持电容器的一端之间。 在启动期间，通过第一至第四控制开关元件向保持电容器提供高电压。

公开(公告)号：US20110157112A1

公开(公告)日：2011-06-30

申请号：US12977941

申请日：2010-12-23

申请人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

发明人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

摘要： A gate signal line driving circuit and a display device includes first and second low voltage application switching elements that supply a low voltage to gate signal lines, a holding capacitor that is connected to a reset target node and supplies an ON signal towards the first and second low voltage application switching elements in a signal low period, first and third control switching elements the one ends of which are connected to the switch input of the first or second low voltage application switching element, and second and fourth control switching elements which each are provided between the switch input of the first or second low voltage application switching element and one end of the holding capacitor. In a startup period, a high voltage is supplied to the holding capacitor through the first to fourth control switching elements.

摘要翻译： 栅极信号线驱动电路和显示装置包括向栅极信号线提供低电压的第一和第二低电压施加开关元件，连接到复位目标节点的保持电容器，并向第一和第二 信号低周期中的低电压应用开关元件，其一端连接到第一或第二低电压应用开关元件的开关输入的第一和第三控制开关元件，以及各自提供的第二和第四控制开关元件 在第一或第二低电压施加开关元件的开关输入和保持电容器的一端之间。 在启动期间，通过第一至第四控制开关元件向保持电容器提供高电压。