公开(公告)号：US20090124080A1

公开(公告)日：2009-05-14

申请号：US12351906

申请日：2009-01-12

申请人： Takashi SHIGEOKA ,  Shoichi Miyazaki

发明人： Takashi SHIGEOKA ,  Shoichi Miyazaki

IPC分类号： H01L21/02

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes.

摘要翻译： 半导体器件包括形成为相同层的半导体衬底，第一存储单元晶体管，第一选择栅极晶体管，第二存储单元晶体管，第二选择栅极晶体管，接触插塞，氧化硅膜和等离子体膜 作为氧化硅膜，并且设置在第一和第三栅电极的上表面之上。

公开(公告)号：US20070138593A1

公开(公告)日：2007-06-21

申请号：US11558692

申请日：2006-11-10

申请人： Takashi Shigeoka ,  Shoichi Miyazaki

发明人： Takashi Shigeoka ,  Shoichi Miyazaki

IPC分类号： H01L29/00

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： A semiconductor device includes a semiconductor substrate, a first memory cell transistor, a first select gate transistor, a second memory cell transistor, a second select gate transistor, a contact plug, silicon oxide films, and plasma films which are formed as the same layer as the silicon oxide films and are provided above upper surfaces of the first and the third gate electrodes.

摘要翻译： 半导体器件包括形成为相同层的半导体衬底，第一存储单元晶体管，第一选择栅极晶体管，第二存储单元晶体管，第二选择栅极晶体管，接触插塞，氧化硅膜和等离子体膜 作为氧化硅膜，并且设置在第一和第三栅电极的上表面之上。

公开(公告)号：US07651912B2

公开(公告)日：2010-01-26

申请号：US11871591

申请日：2007-10-12

申请人： Shoichi Miyazaki

发明人： Shoichi Miyazaki

IPC分类号： H01L21/336

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： A semiconductor device includes a semiconductor substrate having a plurality of element regions and a plurality of element isolation regions in a first direction, a plurality of floating gate electrodes formed via a gate insulating film on the respective element regions, an intergate insulating film formed on the floating gate electrodes, a plurality of control gate electrodes formed on the intergate insulating film so as to extend over the adjacent floating gate electrodes, and an element isolation insulating film formed in the element isolation region and having an upper end located higher than the upper surface of the gate insulating film, the element isolation insulating film including a part formed between the control gate electrodes so that the central sidewall of the element isolation insulating film is located lower than the end of the sidewall of the element isolation insulating film.

摘要翻译： 一种半导体器件包括：具有多个元件区域和多个第一方向的元件隔离区域的半导体基板，经由各元件区域上的栅极绝缘膜形成的多个浮置栅电极，形成在所述栅极绝缘膜上的栅极间绝缘膜 浮置栅极电极，形成在栅极间绝缘膜上的多个控制栅电极，以便在相邻的浮置栅电极之上延伸;以及元件隔离绝缘膜，其形成在元件隔离区域中并且具有位于高于上表面的上端 所述元件隔离绝缘膜包括形成在所述控制栅电极之间的部分，使得所述元件隔离绝缘膜的中心侧壁位于所述元件隔离绝缘膜的侧壁的端部之下。

公开(公告)号：US20070187743A1

公开(公告)日：2007-08-16

申请号：US11656382

申请日：2007-01-23

申请人： Shoichi Miyazaki ,  Hisataka Meguro ,  Fumitaka Arai

发明人： Shoichi Miyazaki ,  Hisataka Meguro ,  Fumitaka Arai

IPC分类号： H01L29/76

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

摘要翻译： 半导体器件包括彼此相对并且形成在选择晶体管形成区域中的一对选择栅极结构，每个选择栅极结构包括形成在半导体衬底上的栅极绝缘膜和形成在栅极电极上的栅电极 栅极绝缘膜和一对存储单元栅极结构组，其形成在一对存储单元形成区域中，在该对存储单元形成区域之间插入选择晶体管形成区域，并且每个存储单元栅极结构组具有以相同间距排列的多个存储单元栅极结构 所述一对选择栅极结构具有彼此相对的侧面，并且至少所述选择栅极结构的每个相对侧的上部是倾斜的。

公开(公告)号：US20060214211A1

公开(公告)日：2006-09-28

申请号：US11347375

申请日：2006-02-06

申请人： Shoichi Miyazaki

发明人： Shoichi Miyazaki

IPC分类号： H01L29/94

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion.

摘要翻译： 半导体器件包括具有第一栅极绝缘膜，第一栅极电极，第二栅极绝缘膜和第二栅极电极的存储单元栅极结构，具有第三栅极绝缘膜的选择栅极结构和包括第三栅极绝缘膜的第三栅极电极 在第一电极部分和第二电极部分之间的第一电极部分，第二电极部分和第三电极部分，形成在半导体衬底的表面区域中的第一杂质扩散层， 所述存储单元栅极结构和所述第一电极部分以及形成在所述半导体衬底的表面区域中并位于对应于所述第一电极部分和所述第二电极部分之间的区域的部分的第二杂质扩散层。

公开(公告)号：US07825453B2

公开(公告)日：2010-11-02

申请号：US11347375

申请日：2006-02-06

申请人： Shoichi Miyazaki

发明人： Shoichi Miyazaki

IPC分类号： H01L27/108

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a memory cell gate structure having a first gate insulating film, a first gate electrode, a second gate insulating film, and a second gate electrode, a select gate structure having a third gate insulating film and a third gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion between the first electrode portion and the second electrode portion, a first impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the memory cell gate structure and the first electrode portion, and a second impurity diffusion layer formed in a surface area of the semiconductor substrate and located at a portion which corresponds to an area between the first electrode portion and second electrode portion.

摘要翻译： 半导体器件包括具有第一栅极绝缘膜，第一栅极电极，第二栅极绝缘膜和第二栅极电极的存储单元栅极结构，具有第三栅极绝缘膜的选择栅极结构和包括第三栅极绝缘膜的第三栅极电极 在第一电极部分和第二电极部分之间的第一电极部分，第二电极部分和第三电极部分，形成在半导体衬底的表面区域中的第一杂质扩散层， 所述存储单元栅极结构和所述第一电极部分以及形成在所述半导体衬底的表面区域中并位于对应于所述第一电极部分和所述第二电极部分之间的区域的部分的第二杂质扩散层。

公开(公告)号：US20080050908A1

公开(公告)日：2008-02-28

申请号：US11877833

申请日：2007-10-24

申请人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

发明人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

IPC分类号： H01L21/4763

CPC分类号： H01L23/485 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充 在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连 层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

公开(公告)号：US20060244018A1

公开(公告)日：2006-11-02

申请号：US11219724

申请日：2005-09-07

申请人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

发明人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

IPC分类号： H01L29/76 ,  H01L23/52

CPC分类号： H01L23/485 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a first surface. First gate electrodes are formed along a first direction on the first surface. Source/drain areas are formed in the first surface and sandwich a channel region. A first interlayer insulating layer fills a region between the first gate electrodes and has the top lower than the tops of the first gate electrodes. A second interlayer insulating layer is formed above the first gate electrodes and the first interlayer insulating layer. Interconnect layers are formed in the second interlayer insulating layer along a direction which intersects the first direction and is insulated from each other. A region between the interconnect layers is filled with the second interlayer insulating layer. A contact plug is formed in the first and second interlayer insulating layers and is in contact with the interconnect layer and the source/drain area.

摘要翻译： 半导体器件包括具有第一表面的半导体衬底。 第一栅电极沿着第一方向在第一表面上形成。 源极/漏极区域形成在第一表面中并夹着沟道区域。 第一层间绝缘层填充第一栅电极之间的区域，并且具有比第一栅电极的顶部低的顶部。 在第一栅电极和第一层间绝缘层的上方形成第二层间绝缘层。 互连层沿着与第一方向相交的方向形成在第二层间绝缘层中并且彼此绝缘。 互连层之间的区域被第二层间绝缘层填充。 接触插塞形成在第一和第二层间绝缘层中并且与互连层和源极/漏极区域接触。

公开(公告)号：US07825497B2

公开(公告)日：2010-11-02

申请号：US12610022

申请日：2009-10-30

申请人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

发明人： Hiroyuki Kutsukake ,  Yasuhiko Matsunaga ,  Shoichi Miyazaki

IPC分类号： H01L23/485

CPC分类号： H01L23/485 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas.

摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的第一表面上沿着第一方向形成两个第一栅电极和在每个第一栅电极下夹着沟道区的源/漏区，形成第一层间绝缘层以填充 在所述第一栅电极之间的区域中，降低所述第一层间绝缘层的顶部，在所述第一层间绝缘层上沉积第二层间绝缘层和所述第一栅电极，使所述第二层间绝缘层的表面平坦化，以及形成互连 层和第一层间绝缘层和第二层间绝缘层中的接触塞，使得接触插塞与互连层和源极/漏极区之一接触。

公开(公告)号：US07718474B2

公开(公告)日：2010-05-18

申请号：US11656382

申请日：2007-01-23

申请人： Shoichi Miyazaki ,  Hisataka Meguro ,  Fumitaka Arai

发明人： Shoichi Miyazaki ,  Hisataka Meguro ,  Fumitaka Arai

IPC分类号： H01L21/335

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

摘要翻译： 半导体器件包括彼此相对并且形成在选择晶体管形成区域中的一对选择栅极结构，每个选择栅极结构包括形成在半导体衬底上的栅极绝缘膜和形成在栅极电极上的栅电极 栅极绝缘膜和一对存储单元栅极结构组，其形成在一对存储单元形成区域中，在该对存储单元形成区域之间插入选择晶体管形成区域，并且每个存储单元栅极结构组具有以相同间距排列的多个存储单元栅极结构 所述一对选择栅极结构具有彼此相对的侧面，并且至少所述选择栅极结构的每个相对侧的上部是倾斜的。