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公开(公告)号：US08719615B2
公开(公告)日：2014-05-06
申请号：US13064316
申请日：2011-03-17
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F9/3887 , G06F9/3893
摘要： A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.
摘要翻译： 半导体器件与某个时钟信号同步地进行操作。 该半导体装置包括用于输出操作控制信息的控制单元，用于存储数据的存储单元，用于根据第一操作控制信息对第一数据执行操作的第一操作单元和用于对第二数据执行操作的第二操作单元 根据第二操作控制信息。 第一操作单元包括多个操作电路。 构成整个运算电路的逻辑门的数量为m。 第二操作单元包括其中逻辑门数为n（n> m）的至少一个操作电路。 操作单元的总延迟或操作单元的总延迟中的每一个被设置为等于或小于时钟信号的周期的值。
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公开(公告)号：US08195975B2
公开(公告)日：2012-06-05
申请号：US12341147
申请日：2008-12-22
IPC分类号： G06F1/04
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal.
摘要翻译： 连接在流水线结构中的多个操作单元对数据进行操作处理。 过程控制单元与系统时钟信号同步地操作，并且在接收到通知过程控制单元来自外部的数据到达的数据通知信号时产生用于控制操作单元的过程控制信号。 时钟控制信号产生单元与系统时钟信号同步地工作，并且在接收到处理控制信号时产生用于控制每个操作单元的时钟供给的时钟控制信号。
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3.发明授权Processing in pipelined computing units with data line and circuit configuration rule signal line 失效用流水线计算单元处理数据线和电路配置规则信号线公开(公告)号：US07653805B2
公开(公告)日：2010-01-26
申请号：US11727134
申请日：2007-03-23
IPC分类号： G06F15/76
CPC分类号： G06F15/7867
摘要： A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of the computing units including: a data line for receiving data; a control line for receiving a rule signal; a circuit information control unit configured to store, before data processing, several circuit information items, and to output a first one of the several circuit information items according to the rule signal received via the control line in a first cycle of the data processing; a processing element configured to construct an execution circuit according to the first circuit information item, to perform a computation using data from the data line, and to output a computation result; a data register for storing the computation result, and for outputting the computation result in a second cycle; and a control register for storing the rule signal and for outputting the rule signal in the second cycle. The semiconductor further includes a controller configured to control output timing of the rule signal to the control line of a first-stage one of the computing units in the pipeline and to control output timing of the data to the data line of the first-stage computing unit in the first cycle, so that the plurality of computing units are operated as a pipeline.
摘要翻译： 用于通过循环执行多个计算来执行数据处理的半导体装置包括通过串联连接多个计算单元而形成的流水线，每个计算单元包括：用于接收数据的数据线; 用于接收规则信号的控制线; 电路信息控制单元，被配置为在数据处理之前存储几个电路信息项，并且在数据处理的第一周期中根据经由控制线接收的规则信号来输出多个电路信息项中的第一个; 处理元件，被配置为构成根据第一电路信息项的执行电路，以使用来自数据线的数据执行计算，并输出计算结果; 数据寄存器，用于存储所述计算结果，并用于在第二周期中输出所述计算结果; 以及用于存储规则信号并在第二周期中输出规则信号的控制寄存器。 半导体还包括控制器，被配置为控制规则信号的输出定时到流水线中的计算单元的第一级的控制线，并且控制数据到第一级计算的数据线的输出定时 单元，使得多个计算单元作为流水线操作。
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公开(公告)号：US07917707B2
公开(公告)日：2011-03-29
申请号：US12052324
申请日：2008-03-20
IPC分类号： G06F12/00
CPC分类号： G06F15/7867
摘要： A semiconductor device includes a plurality of operating units, a controller that controls the plurality of operating units according to predetermined state transition, a first storage that stores data to be processed, a second storage that stores circuit information specifying an operation process performed in the plurality of operating units, a third storage that stores data access information for the first storage and a pointer for the second storage in association with a state of the controller. The controller reads an address and the pointer stored in the third storage according to the state, and transmits the circuit information stored in a region of the second storage specified by the read pointer to the plurality of operating units.
摘要翻译： 半导体器件包括多个操作单元，控制器，其根据预定状态转换来控制多个操作单元;存储要处理数据的第一存储器;存储指定在多个操作中执行的操作处理的电路信息的第二存储器 操作单元的第三存储器，与控制器的状态相关联地存储用于第一存储的数据访问信息的第三存储器和用于第二存储器的指针。 控制器根据状态读取存储在第三存储器中的地址和指针，并将存储在由读指针指定的第二存储区域中的电路信息发送到多个操作单元。
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公开(公告)号：US20070245131A1
公开(公告)日：2007-10-18
申请号：US11727134
申请日：2007-03-23
IPC分类号： G06F15/00
CPC分类号： G06F15/7867
摘要： A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of the computing units including: a data line for receiving data; a control line for receiving a rule signal; a circuit information control unit configured to store, before data processing, several circuit information items, and to output a first one of the several circuit information items according to the rule signal received via the control line in a first cycle of the data processing; a processing element configured to construct an execution circuit according to the first circuit information item, to perform a computation using data from the data line, and to output a computation result; a data register for storing the computation result, and for outputting the computation result in a second cycle; and a control register for storing the rule signal and for outputting the rule signal in the second cycle. The semiconductor further includes a controller configured to control output timing of the rule signal to the control line of a first-stage one of the computing units in the pipeline and to control output timing of the data to the data line of the first-stage computing unit in the first cycle, so that the plurality of computing units are operated as a pipeline.
摘要翻译： 用于通过循环执行多个计算来执行数据处理的半导体装置包括通过串联连接多个计算单元而形成的流水线，每个计算单元包括：用于接收数据的数据线; 用于接收规则信号的控制线; 电路信息控制单元，被配置为在数据处理之前存储几个电路信息项，并且在数据处理的第一周期中根据经由控制线接收的规则信号来输出多个电路信息项中的第一个; 处理元件，被配置为构成根据第一电路信息项的执行电路，以使用来自数据线的数据执行计算，并输出计算结果; 数据寄存器，用于存储所述计算结果，并用于在第二周期中输出所述计算结果; 以及用于存储规则信号并在第二周期中输出规则信号的控制寄存器。 半导体还包括控制器，被配置为控制规则信号的输出定时到流水线中的计算单元的第一级的控制线，并且控制数据到第一级计算的数据线的输出定时 单元，使得多个计算单元作为流水线操作。
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公开(公告)号：US20110289339A1
公开(公告)日：2011-11-24
申请号：US13064316
申请日：2011-03-17
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F9/3887 , G06F9/3893
摘要： A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.
摘要翻译： 半导体器件与某个时钟信号同步地进行操作。 该半导体装置包括用于输出操作控制信息的控制单元，用于存储数据的存储单元，用于根据第一操作控制信息对第一数据执行操作的第一操作单元和用于对第二数据执行操作的第二操作单元 根据第二操作控制信息。 第一操作单元包括多个操作电路。 构成整个运算电路的逻辑门的数量为m。 第二操作单元包括其中逻辑门数为n（n> m）的至少一个操作电路。 操作单元的总延迟或操作单元的总延迟中的每一个被设置为等于或小于时钟信号的周期的值。
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公开(公告)号：US20090172458A1
公开(公告)日：2009-07-02
申请号：US12341147
申请日：2008-12-22
IPC分类号： G06F1/12
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
摘要： A plurality of operation units connected in a pipeline structure performs an operation processing on data. A process control unit operates in synchronization with a system clock signal and generates a process control signal for controlling the operation units upon receiving a data notification signal that notifies the process control unit of an arrival of data from outside. A clock-control signal generating unit operates in synchronization with the system clock signal and generates a clock control signal for controlling a clock supply to each of the operation units upon receiving the process control signal.
摘要翻译： 连接在流水线结构中的多个操作单元对数据进行操作处理。 过程控制单元与系统时钟信号同步地操作，并且在接收到通知过程控制单元来自外部的数据到达的数据通知信号时产生用于控制操作单元的过程控制信号。 时钟控制信号产生单元与系统时钟信号同步地工作，并且在接收到处理控制信号时产生用于控制每个操作单元的时钟供给的时钟控制信号。
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公开(公告)号：US08631173B2
公开(公告)日：2014-01-14
申请号：US12050899
申请日：2008-03-18
申请人： Takashi Yoshikawa , Shigehiro Asano
发明人： Takashi Yoshikawa , Shigehiro Asano
CPC分类号： G06F9/3001 , G06F9/3867 , G06F9/3879 , G06F15/7832 , Y02D10/12 , Y02D10/13
摘要： A semiconductor device includes a first arithmetic engine which executes a first arithmetic process in every cycle and outputs first data representing the result of the first arithmetic process and a first valid signal representing a first or second value in every cycle, and a second arithmetic engine which executes a second arithmetic process in every cycle and outputs second data representing the result of the second arithmetic process and a second valid signal representing the first or second value in every cycle. The device also includes an inter-arithmetic-engine buffer which is used to exchange the first data and the second data between the first and second arithmetic engines, enables write of the first or second data if the first or second valid signal indicates the first value, and inhibits write of the first or second data if the first or second valid signal indicates the second value.
摘要翻译： 半导体器件包括：第一运算引擎，其在每个周期中执行第一运算处理，并且输出表示第一运算处理结果的第一数据和表示每个周期中的第一或第二值的第一有效信号;以及第二运算引擎， 在每个周期中执行第二运算处理，并且在每个周期中输出表示第二运算处理结果的第二数据和表示第一或第二值的第二有效信号。 该装置还包括一个算术引擎缓冲器，用于在第一和第二算术引擎之间交换第一数据和第二数据，如果第一或第二有效信号指示第一值，则能够写入第一或第二数据 并且如果第一或第二有效信号指示第二值，则禁止写入第一或第二数据。
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公开(公告)号：US20070198758A1
公开(公告)日：2007-08-23
申请号：US11517327
申请日：2006-09-08
申请人： Shigehiro Asano , Takashi Yoshikawa
发明人： Shigehiro Asano , Takashi Yoshikawa
IPC分类号： G06F13/00
CPC分类号： G06F13/368
摘要： A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.
摘要翻译： 用于在总线主机和总线从站之间传送信息的总线装置包括：能够通过流水线处理从总线主机向总线从机传输信息的多个流水线寄存器; 以及管理每个流水线寄存器的多个管理装置。 此外，管理装置包括：保持状态保持单元，其将保持状态保持为指示与管理装置对应的当前级的流水线寄存器是否保存信息的信息; 相邻级的保持状态指定单元，其指定向当前级的流水线寄存器发送信息的前一级的流水线寄存器的保持状态，以及发送来自当前级的流水线寄存器的信息的后级的流水线寄存器的保持状态; 以及传送控制单元，其确定由相应流水线寄存器保存的信息是否被传送。
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10.发明授权公开(公告)号：US07818546B2
公开(公告)日：2010-10-19
申请号：US11517327
申请日：2006-09-08
申请人： Shigehiro Asano , Takashi Yoshikawa
发明人： Shigehiro Asano , Takashi Yoshikawa
CPC分类号： G06F13/368
摘要： A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.
摘要翻译： 用于在总线主机和总线从站之间传送信息的总线装置包括：能够通过流水线处理从总线主机向总线从机传输信息的多个流水线寄存器; 以及管理每个流水线寄存器的多个管理装置。 此外，管理装置包括：保持状态保持单元，其将保持状态保持为指示与管理装置对应的当前级的流水线寄存器是否保存信息的信息; 相邻级的保持状态指定单元，其指定向当前级的流水线寄存器发送信息的前一级的流水线寄存器的保持状态，以及发送来自当前级的流水线寄存器的信息的后级的流水线寄存器的保持状态; 以及传送控制单元，其确定由相应流水线寄存器保存的信息是否被传送。
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