公开(公告)号：US08253188B2

公开(公告)日：2012-08-28

申请号：US12728788

申请日：2010-03-22

申请人： Takeshi Kamigaichi ,  Satoshi Nagashima ,  Kenji Aoyama

发明人： Takeshi Kamigaichi ,  Satoshi Nagashima ,  Kenji Aoyama

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11529 ,  H01L27/11519 ,  H01L27/11526

摘要： A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.

摘要翻译： 一种半导体存储装置，包括半导体衬底，第一绝缘体，层叠绝缘体，其包括具有比第一绝缘体的电荷多的固定电荷的第二绝缘体，单层绝缘体，半导体衬底和第一绝缘体之间的存储单元， 通过空腔部分从相邻的存储单元分离的单元，包括隧道绝缘体，电荷累积层，绝缘体和控制栅电极，在半导体衬底和第一绝缘体之间的第一选择栅极晶体管，第二选择栅极晶体管 在所述半导体衬底和所述第一绝缘体之间，在一个存储单元和所述第一选择栅极晶体管之间，并且与所述层叠绝缘体在其存储单元侧的第一侧面接触;以及所述半导体之间的高压外围电路晶体管 基板和第一绝缘体，并与一侧的单层绝缘体接触 面对。

公开(公告)号：US20100237398A1

公开(公告)日：2010-09-23

申请号：US12728788

申请日：2010-03-22

申请人： Takeshi Kamigaichi ,  Satoshi Nagashima ,  Kenji Aoyama

发明人： Takeshi Kamigaichi ,  Satoshi Nagashima ,  Kenji Aoyama

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11529 ,  H01L27/11519 ,  H01L27/11526

摘要： A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.

摘要翻译： 一种半导体存储装置，包括半导体衬底，第一绝缘体，层叠绝缘体，其包括具有比第一绝缘体的电荷多的固定电荷的第二绝缘体，单层绝缘体，半导体衬底和第一绝缘体之间的存储单元， 通过空腔部分从相邻的存储单元分离的单元，包括隧道绝缘体，电荷累积层，绝缘体和控制栅电极，在半导体衬底和第一绝缘体之间的第一选择栅极晶体管，第二选择栅极晶体管 在所述半导体衬底和所述第一绝缘体之间，在一个存储单元和所述第一选择栅极晶体管之间，并且与所述层叠绝缘体在其存储单元侧的第一侧面接触;以及所述半导体之间的高压外围电路晶体管 基板和第一绝缘体，并与一侧的单层绝缘体接触 面对。

公开(公告)号：US08253199B2

公开(公告)日：2012-08-28

申请号：US12350658

申请日：2009-01-08

申请人： Kyoko Ando ,  Satoshi Nagashima ,  Kenji Aoyama

发明人： Kyoko Ando ,  Satoshi Nagashima ,  Kenji Aoyama

IPC分类号： H01L27/12

CPC分类号： H01L29/42324 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film.

摘要翻译： 半导体存储器件具有半导体衬底，以预定间隔形成在半导体衬底上的多条字线，选择晶体管布置在多个字线中的每一个的两侧中，其中选择晶体管和 字线的相邻一方的字线宽度不小于每条字线的宽度的三倍，形成为覆盖字线的上表面并选择晶体管的层间绝缘膜，第一空腔部分位于每对相邻的 所述字线中的一个并且其上部被所述层间绝缘膜覆盖;第二空腔部分，形成在所述字线的与所述选择晶体管相对并且其上部被覆盖的相邻的字线的侧壁部分处 层间绝缘膜和形成在每个选择晶体管的侧壁部分的第三空腔部分 并且其上部被层间绝缘膜覆盖。

公开(公告)号：US08053825B2

公开(公告)日：2011-11-08

申请号：US11927799

申请日：2007-10-30

申请人： Kenji Aoyama ,  Satoshi Nagashima

发明人： Kenji Aoyama ,  Satoshi Nagashima

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.

摘要翻译： 层叠栅极非易失性半导体存储器至少包括形成在半导体衬底上的存储单元晶体管和选择栅极晶体管。 存储单元晶体管包括由层间绝缘层下方的半导体材料制成的浮置栅极和由层间绝缘层上方的硅化物制成的控制栅极。 选择栅极晶体管包括由半导体材料制成的半导体层，由硅化物制成的硅化物层和由不经过硅化处理的导电材料制成的导电层，该导电层通过层间绝缘膜形成，以将半导体 层和硅化物层。

公开(公告)号：US07868376B2

公开(公告)日：2011-01-11

申请号：US12354271

申请日：2009-01-15

申请人： Kenji Aoyama ,  Hisataka Meguro ,  Satoshi Nagashima

发明人： Kenji Aoyama ,  Hisataka Meguro ,  Satoshi Nagashima

IPC分类号： H01L29/792

CPC分类号： H01L21/28247 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

公开(公告)号：US20090218614A1

公开(公告)日：2009-09-03

申请号：US12354271

申请日：2009-01-15

申请人： Kenji AOYAMA ,  Hisataka Meguro ,  Satoshi Nagashima

发明人： Kenji AOYAMA ,  Hisataka Meguro ,  Satoshi Nagashima

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28247 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

摘要翻译： 半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜 所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及 选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分， 与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

公开(公告)号：US20090206391A1

公开(公告)日：2009-08-20

申请号：US12350658

申请日：2009-01-08

申请人： Kyoko ANDO ,  Satoshi Nagashima ,  Kenji Aoyama

发明人： Kyoko ANDO ,  Satoshi Nagashima ,  Kenji Aoyama

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion is covered with the interlayer insulating film.

摘要翻译： 半导体存储器件具有半导体衬底，以预定间隔形成在半导体衬底上的多条字线，选择晶体管布置在多个字线中的每一个的两侧中，其中选择晶体管和 字线的相邻一方的字线宽度不小于每条字线的宽度的三倍，形成为覆盖字线的上表面并选择晶体管的层间绝缘膜，第一空腔部分位于每对相邻的 所述字线中的一个并且其上部被所述层间绝缘膜覆盖;第二空腔部分，形成在所述字线的与所述选择晶体管相对并且其上部被覆盖的相邻的字线的侧壁部分处 层间绝缘膜和形成在每个选择晶体管的侧壁部分的第三空腔部分 并且其上部被层间绝缘膜覆盖。

公开(公告)号：US20120012916A1

公开(公告)日：2012-01-19

申请号：US13137918

申请日：2011-09-21

申请人： Kenji Aoyama ,  Satoshi Nagashima

发明人： Kenji Aoyama ,  Satoshi Nagashima

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A stacked gate nonvolatile semiconductor memory includes at least a memory cell transistor and a selective gate transistor which are formed on a semiconductor substrate. The memory cell transistor includes a floating gate made of a semiconductor material below an interlayer insulating layer and a control gate made of a silicide above the interlayer insulating layer. The selective gate transistor includes a semiconductor layer made of the semiconductor material, a silicide layer made of the silicide and a conductive layer made of a conductive material not subject to silicide process which is formed through the interlayer insulating film so as to electrically connect the semiconductor layer and the silicide layer.

摘要翻译： 层叠栅极非易失性半导体存储器至少包括形成在半导体衬底上的存储单元晶体管和选择栅极晶体管。 存储单元晶体管包括由层间绝缘层下方的半导体材料制成的浮置栅极和由层间绝缘层上方的硅化物制成的控制栅极。 选择栅晶体管包括由半导体材料制成的半导体层，由硅化物制成的硅化物层和由不经过硅化处理的导电材料制成的导电层，该导电层通过层间绝缘膜形成，以将半导体 层和硅化物层。

公开(公告)号：US08071449B2

公开(公告)日：2011-12-06

申请号：US12926677

申请日：2010-12-03

申请人： Kenji Aoyama ,  Hisataka Meguro ,  Satoshi Nagashima

发明人： Kenji Aoyama ,  Hisataka Meguro ,  Satoshi Nagashima

IPC分类号： H01L21/336

CPC分类号： H01L21/28247 ,  H01L21/76229 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568

摘要： A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

摘要翻译： 半导体存储装置具有在半导体衬底上形成有预定间隔的多个字线，设置在多个字线的端部的选择晶体管，形成为覆盖字线的侧面的第一绝缘膜 所述选择晶体管的侧面以及所述字线之间的所述半导体基板的表面，形成在所述第一绝缘膜上的高电容率膜，形成为覆盖所述字线的上表面的第二绝缘膜，以及 选择晶体管，位于字线之间并被高电容率膜和第二绝缘膜包围的第一气隙部分和经由第一绝缘膜和高介电常数膜形成的第二气隙部分， 与选择晶体管相邻的字线相对的选择晶体管的侧壁部分，第二气隙部分的上部被第二i 记录膜。

公开(公告)号：US08629528B2

公开(公告)日：2014-01-14

申请号：US13557295

申请日：2012-07-25

申请人： Kyoko Ando ,  Satoshi Nagashima ,  Kenji Aoyama

发明人： Kyoko Ando ,  Satoshi Nagashima ,  Kenji Aoyama

IPC分类号： H01L21/70

CPC分类号： H01L29/42324 ,  H01L21/76229 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/66825 ,  H01L29/7883

摘要： According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.

摘要翻译： 根据一个实施例，半导体存储器件包括以预定间隔形成在半导体衬底上的多个字线，选择排列在多个字线的至少一侧的晶体管，形成为覆盖所述多个字线的上表面的层间绝缘膜 字线和选择晶体管，位于每对相邻字线之间并由层间绝缘膜覆盖的第一气隙，位于与选择晶体管相邻的字线的第一侧壁部分处的第二气隙 被层间绝缘膜覆盖，面向选择晶体管的第一侧壁部分和位于每个选择晶体管的第二侧壁部分并被层间绝缘膜覆盖的第三气隙。 第一，第二和第三气隙充满空气。