Polymer pattern forming method
    1.
    发明授权
    Polymer pattern forming method 失效
    聚合物图案形成方法

    公开(公告)号:US06372411B1

    公开(公告)日:2002-04-16

    申请号:US09261463

    申请日:1999-02-24

    IPC分类号: G03F700

    CPC分类号: G03F7/38 G03F7/027

    摘要: A polymer pattern forming method including the steps of (a) generating radicals in a pattern forming region of a matrix layer which uniformly contains a radical generating agent, thereby forming a patterned latent image due to the radicals in the pattern forming region; and (b) bringing a monomer which polymerizes by radical polymerization into contact with the matrix layer in which the patterned latent image has been or is being formed, to have the radicals which have been or are being generated induce a chain addition polymerization of the monomer so as to form a polymer pattern on the pattern forming region.

    摘要翻译: 一种聚合物图案形成方法,包括以下步骤:(a)在均匀地含有自由基生成剂的基质层的图案形成区域中产生自由基,由此在图案形成区域中由于自由基而形成图案化的潜像; 和(b)使通过自由基聚合聚合的单体与已经或正在形成图案化潜像的基质层接触,使已经或正在生成的基团引起单体的链加成聚合 以在图案形成区域上形成聚合物图案。

    Optical waveguide made of polymer material and a method of fabricating the same
    2.
    发明授权
    Optical waveguide made of polymer material and a method of fabricating the same 失效
    由聚合物材料制成的光波导及其制造方法

    公开(公告)号:US06327415B1

    公开(公告)日:2001-12-04

    申请号:US09531322

    申请日:2000-03-20

    IPC分类号: G02B600

    摘要: An optical waveguide having a clad and a core, the core being made of polymer material containing a repetitive unit having formula (1), (2) or (3): Each of these polymer materials has a higher glass transition temperature and lower water absorption than those of deuterated PMMA, has a transparency equivalent with that of deuterated PMMA, and shows neither light absorption nor scattering in the operating wavelength region. An optical waveguide with a core fabricated using these polymer materials is high in heat resistance and low in water absorption. Thus using the waveguide will successfully provide optical communication elements with an advanced durability against the environment.

    摘要翻译: 一种具有包层和芯的光波导,该芯由含有式(1),(2)或(3)的重复单元的聚合物材料制成:这些聚合物材料中的每一种具有较高的玻璃化转变温度和较低的吸水率 与氘代PMMA相比,具有与氘代PMMA相当的透明度,并且在工作波长区域中既不显示光吸收也不显示散射。 使用这些聚合物材料制造的具有芯的光波导具有高的耐热性和低吸水性。 因此,使用波导将成功地为光通信元件提供对环境的高级耐久性。

    Etching method, method of fabricating metal film structure, and etching structure
    4.
    发明授权
    Etching method, method of fabricating metal film structure, and etching structure 失效
    蚀刻方法,金属膜结构的制造方法和蚀刻结构

    公开(公告)号:US07393791B2

    公开(公告)日:2008-07-01

    申请号:US11512341

    申请日:2006-08-30

    IPC分类号: H01L21/302

    摘要: There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a substrate, a protective film formed on the substrate, a photoresist layer formed on the protective film, and a hole formed throughout the photoresist layer. The hole comprises an opening formed in the photoresist layer surface and a hollow linked to the opening in the thickness direction of the photoresist layer and reaching the protective film. ICP-RIE is performed under conditions such that (1) ICP power is 20 to 100 W, (2) RIE power is 5 to 50 W, and (3) the pressure in the etching chamber is 1 to 100 mTorr.

    摘要翻译: 提供一种蚀刻方法,其中通过ICP-RIE去除存在于衬底结构的蚀刻目的地区域中的保护膜,以形成衬底的主表面的曝光区域。 衬底结构包括衬底,形成在衬底上的保护膜,形成在保护膜上的光致抗蚀剂层和在整个光致抗蚀剂层上形成的孔。 孔包括形成在光致抗蚀剂层表面中的开口和在光致抗蚀剂层的厚度方向上连接到开口的中空并到达保护膜。 ICP-RIE在(1)ICP功率为20〜100W的条件下进行,(2)RIE功率为5〜50W,(3)蚀刻室内的压力为1〜100mTorr。

    Ohmic electrode, method of manufacturing Ohmic electrode, field effect transistor, method of manufacturing field effect transistor, and semiconductor device
    5.
    发明申请
    Ohmic electrode, method of manufacturing Ohmic electrode, field effect transistor, method of manufacturing field effect transistor, and semiconductor device 有权
    欧姆电极,制造欧姆电极,场效应晶体管,制造场效应晶体管的方法和半导体器件

    公开(公告)号:US20070051978A1

    公开(公告)日:2007-03-08

    申请号:US11505301

    申请日:2006-08-17

    IPC分类号: H01L29/739

    摘要: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

    摘要翻译: 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。

    Etching structure
    6.
    发明申请
    Etching structure 审中-公开
    蚀刻结构

    公开(公告)号:US20080241469A1

    公开(公告)日:2008-10-02

    申请号:US12153867

    申请日:2008-05-27

    IPC分类号: B32B7/00

    摘要: An etching structure includes a substrate, a to be etched filmcovering the principal surface of the substrate, and an exposure region exposing the principal surface of the substrate and obtained by removing a part of the to be etched film. A region of the to be etched film constitutes a peripheral region surrounding the exposure region. Another region of the to be etched film outside the peripheral region constitutes a flat region. The film thickness of the to be etched film increases as the distance from the exposure region increases, such that the inclination of the outline of the cross section of the to be etched film that exists within the peripheral region decreases as the distance from the exposure region increases. The to be etched film has a side wall that extends perpendicularly to the principal surface at a boundary between the peripheral region and the flat region.

    摘要翻译: 蚀刻结构包括:衬底,待蚀刻的膜覆盖衬底的主表面;以及暴露区域,暴露衬底的主表面并通过去除被蚀刻膜的一部分而获得。 被蚀刻膜的区域构成围绕曝光区域的周边区域。 要在周边区域外的被蚀刻膜的另一区域构成平坦区域。 被蚀刻膜的膜厚随着与曝光区域的距离增大而增加,使得存在于周边区域内的被蚀刻膜的截面的轮廓的倾斜度随着与曝光区域的距离而减小 增加 要被蚀刻的膜具有在周边区域和平坦区域之间的边界处垂直于主表面延伸的侧壁。

    Method of manufacturing field effect transistor having Ohmic electrode in a recess
    7.
    发明授权
    Method of manufacturing field effect transistor having Ohmic electrode in a recess 有权
    在凹槽中制造具有欧姆电极的场效应晶体管的方法

    公开(公告)号:US08202794B2

    公开(公告)日:2012-06-19

    申请号:US13064637

    申请日:2011-04-05

    摘要: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

    摘要翻译: 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。

    Field effect transistor having Ohmic electrode in a recess
    8.
    发明授权
    Field effect transistor having Ohmic electrode in a recess 有权
    在凹槽中具有欧姆电极的场效应晶体管

    公开(公告)号:US07923753B2

    公开(公告)日:2011-04-12

    申请号:US11505301

    申请日:2006-08-17

    摘要: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

    摘要翻译: 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。

    Method of manufacturing field effect transistor having Ohmic electrode in a recess
    9.
    发明申请
    Method of manufacturing field effect transistor having Ohmic electrode in a recess 有权
    在凹槽中制造具有欧姆电极的场效应晶体管的方法

    公开(公告)号:US20110189826A1

    公开(公告)日:2011-08-04

    申请号:US13064637

    申请日:2011-04-05

    IPC分类号: H01L21/338

    摘要: The contact resistance between an Ohmic electrode and an electron transit layer is reduced compared with a case in which the Ohmic electrode is provided to a depth less than the heterointerface. As a result, for an Ohmic electrode provided in a structure comprising an electron transit layer formed of a first semiconductor layer formed on a substrate, an electron supply layer comprising a second semiconductor layer forming a heterojunction with the electron transit layer and having a smaller electron affinity than the first semiconductor layer, and a two-dimensional electron layer induced in the electron transit layer in the vicinity of the heterointerface, the end portion of the Ohmic electrode is positioned in the electron transit layer in penetration into the electron supply layer at a depth equal to or greater than the heterointerface.

    摘要翻译: 与将欧姆电极提供到比异质界面更深的情况相比,欧姆电极和电子转移层之间的接触电阻降低。 结果,对于在由形成在基板上的第一半导体层形成的电子转移层的结构中提供的欧姆电极,包括与电子转移层形成异质结并具有较小电子的第二半导体层的电子供给层 亲和性比第一半导体层和在异质界面附近的电子转移层中感应的二维电子层,欧姆电极的端部位于电子转移层中,在电子转移层中以 深度等于或大于异质界面。

    Etching method, method of fabricating metal film structure, and etching structure
    10.
    发明申请
    Etching method, method of fabricating metal film structure, and etching structure 失效
    蚀刻方法,金属膜结构的制造方法和蚀刻结构

    公开(公告)号:US20070049031A1

    公开(公告)日:2007-03-01

    申请号:US11512341

    申请日:2006-08-30

    IPC分类号: H01L21/302

    摘要: There is provided an etching method in which a protective film existing in an etching-destined region of a substrate structure is removed by means of ICP-RIE to form an exposure region of the principal surface of the substrate. The substrate structure comprises a substrate, a protective film formed on the substrate, a photoresist layer formed on the protective film, and a hole formed throughout the photoresist layer. The hole comprises an opening formed in the photoresist layer surface and a hollow linked to the opening in the thickness direction of the photoresist layer and reaching the protective film. ICP-RIE is performed under conditions such that (1) ICP power is 20 to 100 W, (2) RIE power is 5 to 50 W, and (3) the pressure in the etching chamber is 1 to 100 mTorr.

    摘要翻译: 提供一种蚀刻方法,其中通过ICP-RIE去除存在于衬底结构的蚀刻目的地区域中的保护膜,以形成衬底的主表面的曝光区域。 衬底结构包括衬底,形成在衬底上的保护膜,形成在保护膜上的光致抗蚀剂层和在整个光致抗蚀剂层上形成的孔。 孔包括形成在光致抗蚀剂层表面中的开口和在光致抗蚀剂层的厚度方向上连接到开口的中空并到达保护膜。 ICP-RIE在(1)ICP功率为20〜100W的条件下进行,(2)RIE功率为5〜50W,(3)蚀刻室内的压力为1〜100mTorr。