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公开(公告)号：US4947411A
公开(公告)日：1990-08-07
申请号：US123553
申请日：1987-11-20
CPC分类号： H03K23/66
摘要： A clock frequency divider for generating a basic clock signal which provides operation timing for a semiconductor integrated circuit operating in accordance with a program. The clock frequency divider comprises a frequency-dividing factor register for storing a frequency-dividing factor which can be rewritten by the program, and a frequency-dividing circuit for frequency-dividing a source clock signal having a fixed frequency in accordance with the frequency-dividing factor stored in the frequency-dividing factor register, whereby a basic clock which provides a processing rate optimum for a program to be executed being obtained.
摘要翻译： 一种用于产生基本时钟信号的时钟分频器，其为根据程序操作的半导体集成电路提供操作定时。 时钟分频器包括：分频因子寄存器，用于存储可由程序重写的分频因子;以及分频电路，用于根据频率分频因子对具有固定频率的源时钟信号进行分频， 存储在分频因子寄存器中的分频因子，从而获得提供对要执行的程序最佳的处理速率的基本时钟。
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公开(公告)号：US4914616A
公开(公告)日：1990-04-03
申请号：US131864
申请日：1987-12-11
CPC分类号： G06F7/5055
摘要： As the incrementer of the invention comprises a shift register for its lower order bits, while its higher bit portions are constructed in the same way as a conventional incrementer, the incrementer can give output signals directly to a memory and the like without the necessity of decoding the same, and the incrementer is free from carry propagation delay possibilities, which assures an improved rate of operation of the incrementer as a whole.
摘要翻译： 由于本发明的增量器包括用于其较低阶位的移位寄存器，而其较高位部分以与常规增量器相同的方式构造，所以递增器可以将输出信号直接提供给存储器等而不需要解码 相同，并且增量器没有进位传播延迟的可能性，这保证了整体上增量器的操作速率的提高。
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3.发明授权
公开(公告)号：US5276889A
公开(公告)日：1994-01-04
申请号：US543273
申请日：1990-06-25
申请人： Taketora Shiraishi , Eiichi Teraoka , Toru Kengaku
发明人： Taketora Shiraishi , Eiichi Teraoka , Toru Kengaku
CPC分类号： G06F1/3215 , G06F1/3275 , G06F9/3836 , Y02B60/1225 , Y02B60/1228 , Y02B60/32
摘要： A microprocessor, including a synchronous type memory having several parts, includes a power saving feature that places at least some parts of the memory in a non-operating state when instructions not requiring access to the memory are executed. An enable signal is generated when access is not required and a signal supplying circuit supplies a synchronous signal when the enable signal is not generated and supplies a signal in a predetermined state to place at least some parts or all parts of the memory in the non-operating state to reduce power consumption.
摘要翻译： 包括具有若干部分的同步型存储器的微处理器包括省电功能，其中当执行不需要访问存储器的指令时，将存储器的至少一些部分置于非操作状态。 当不需要访问时产生使能信号，并且当不产生使能信号时信号供给电路提供同步信号，并且提供处于预定状态的信号以将存储器的至少一部分或全部部分放置在非易失性存储器中， 运行状态降低功耗。
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公开(公告)号：US06601177B1
公开(公告)日：2003-07-29
申请号：US09636553
申请日：2000-08-11
IPC分类号： G06F126
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/3203 , Y02D10/172
摘要： A semiconductor integrated circuit including circuit groups and driving the circuit groups with respective power supply voltages, digital-to-analog converters that supply the power supply voltages to the circuit groups, and delay measurement circuits that measure delays of circuit element of the circuit groups. This semiconductor integrated circuit includes a central processing unit that establishes settings of registers based on measurements by the delay measurement circuits to control each of the power supply voltages.
摘要翻译： 一种半导体集成电路，包括电路组和驱动具有相应电源电压的电路组，向电路组提供电源电压的数模转换器，以及延迟测量电路组电路元件延迟的测量电路。 该半导体集成电路包括中央处理单元，其基于延迟测量电路的测量建立寄存器的设置，以控制每个电源电压。
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