公开(公告)号：US07216274B2

公开(公告)日：2007-05-08

申请号：US10609254

申请日：2003-06-26

申请人： Talal K. Jaber ,  Srinivas Patil ,  Larry E. Thatcher ,  Chih-Jen M. Lin ,  Anil K. Sabbavarapu ,  David M. Wu ,  Madhukar K. Reddy

发明人： Talal K. Jaber ,  Srinivas Patil ,  Larry E. Thatcher ,  Chih-Jen M. Lin ,  Anil K. Sabbavarapu ,  David M. Wu ,  Madhukar K. Reddy

IPC分类号： G01R31/28

CPC分类号： G01R31/318552 ,  G01R31/318594 ,  G06F11/2236

摘要： A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

摘要翻译： 用于测试复杂集成电路的测试架构，其中每个功能单元可以独立于其他功能单元进行测试。 本发明的实施例允许功能单元的测试以比处理器的其它部分更慢或更快的时钟速度发生，而不会引起延迟或其他不利的定时效应。

公开(公告)号：US06815977B2

公开(公告)日：2004-11-09

申请号：US10328203

申请日：2002-12-23

申请人： Anil K. Sabbavarapu ,  Talal K. Jaber ,  Grant W. McFarland ,  Paven R. Sunkerneni ,  David M. Wu

发明人： Anil K. Sabbavarapu ,  Talal K. Jaber ,  Grant W. McFarland ,  Paven R. Sunkerneni ,  David M. Wu

IPC分类号： H03K1900

CPC分类号： G01R31/318541 ,  G01R31/318552

摘要： According to some embodiments, a circuit includes a Domino state element, a master latch to receive a first clock signal and to store a value in the Domino state element in response to the first clock signal, and a slave latch to receive a second clock signal and to output the value in response to the second clock signal. Some embodiments provide a first state element coupled to a first node, a master latch coupled to the first state element, the master latch to receive a first storage signal, a first load signal, a first clock signal and a first scan value signal, a second state element coupled to a second node, the second node sequential to the first node, and a slave latch coupled to the second state element, the slave latch to receive a second storage signal, a second load signal, a second clock signal and a second scan value signal.

摘要翻译： 根据一些实施例，电路包括Domino状态元件，主锁存器，用于接收第一时钟信号并且响应于第一时钟信号在Domino状态元件中存储值;以及从锁存器，用于接收第二时钟信号 并且响应于第二时钟信号而输出该值。 一些实施例提供耦合到第一节点的第一状态单元，耦合到第一状态单元的主锁存器，主锁存器以接收第一存储信号，第一负载信号，第一时钟信号和第一扫描值信号， 耦合到第二节点的第二状态元件，连接到第一节点的第二节点和耦合到第二状态元件的从锁存器，从锁存器接收第二存储信号，第二负载信号，第二时钟信号和 第二扫描值信号。

公开(公告)号：US08321730B2

公开(公告)日：2012-11-27

申请号：US12648812

申请日：2009-12-29

申请人： Talal K. Jaber ,  David M. Wu

发明人： Talal K. Jaber ,  David M. Wu

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318575 ,  G01R31/318541

摘要： A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.

摘要翻译： 通常会提供扫描结构和设计方法，显着减少扫描面积和功耗开销。 在这方面，引入了包括多个组合逻辑云，与组合逻辑云耦合的扫描单元，扫描单元以加载测试向量的装置，其中扫描单元包括多个第一类型扫描单元和第二类型扫描单元 与单独的组合逻辑云输出顺序耦合，以及第一扫描时钟和第二扫描时钟，其中第一扫描时钟控制第一类扫描单元，第二扫描时钟控制第二类扫描单元。 还描述和要求保护其他实施例。

公开(公告)号：US20110161759A1

公开(公告)日：2011-06-30

申请号：US12648812

申请日：2009-12-29

申请人： Talal K. Jaber ,  David M. Wu

发明人： Talal K. Jaber ,  David M. Wu

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318575 ,  G01R31/318541

摘要： A scan architecture and design methodology yielding significant reduction in scan area and power overhead is generally presented. In this regard, an apparatus is introduced comprising a plurality of combinatorial logic clouds, scan cells coupled with the combinatorial logic clouds, the scan cells to load test vectors, wherein the scan cells comprise a plurality of first type scan cells and second type scan cells sequentially coupled with separate combinatorial logic cloud outputs, and a first scan clock and a second scan clock, wherein the first scan clock controls the first type scan cells and the second scan clock controls the second type scan cells. Other embodiments are also described and claimed.

摘要翻译： 通常会提供扫描结构和设计方法，显着减少扫描面积和功耗开销。 在这方面，引入了包括多个组合逻辑云，与组合逻辑云耦合的扫描单元，扫描单元以加载测试向量的装置，其中扫描单元包括多个第一类型扫描单元和第二类型扫描单元 与单独的组合逻辑云输出顺序耦合，以及第一扫描时钟和第二扫描时钟，其中第一扫描时钟控制第一类扫描单元，第二扫描时钟控制第二类扫描单元。 还描述和要求保护其他实施例。

公开(公告)号：US07370249B2

公开(公告)日：2008-05-06

申请号：US10874718

申请日：2004-06-22

申请人： Zhuoyu Bao ,  David M. Wu ,  Chih-Jen M. Lin

发明人： Zhuoyu Bao ,  David M. Wu ,  Chih-Jen M. Lin

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C2029/5602

摘要： A technique for testing a memory array. More particularly, embodiments of the invention relate to a memory array testing architecture in which a memory array within a device under test (DUT) is able to be tested at speeds substantially similar to those under typical operating conditions of the memory array without incurring significant die real estate and power penalties.

摘要翻译： 用于测试存储器阵列的技术。 更具体地，本发明的实施例涉及一种存储器阵列测试架构，其中在被测器件（DUT）内的存储器阵列能够以与存储器阵列的典型工作条件基本相似的速度进行测试，而不会导致显着的裸片 房地产和权力罚款。

公开(公告)号：US20090187799A1

公开(公告)日：2009-07-23

申请号：US12010000

申请日：2008-01-23

申请人： Talal Jaber ,  David M. Wu ,  Ming Zhang

发明人： Talal Jaber ,  David M. Wu ,  Ming Zhang

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547 ,  G01R31/31858 ,  G06F11/2236

摘要： In one embodiment, the present invention includes a processor having a plurality of logical units to perform operations on data. Each unit may include a multiple input shift register (MISR) at an input of the logical unit to collect and compress data from input signals to the unit. In turn, each MISR may includes bit cells, each having a first cell to receive incoming data and controlled by a first clock signal, a second cell to receive an output of the first cell and controlled by a second clock signal, a mask cell to receive an output of the second cell and to generate a mask signal responsive to a mask clock signal, and a multiplexer coupled between the first and second cells. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括具有多个逻辑单元以对数据执行操作的处理器。 每个单元可以在逻辑单元的输入处包括多输入移位寄存器（MISR），以将数据从输入信号收集和压缩到单元。 反过来，每个MISR可以包括位单元，每个位单元具有接收输入数据并由第一时钟信号控制的第一单元，第二单元接收第一单元的输出并由第二时钟信号控制;掩模单元， 接收所述第二单元的输出并且响应于屏蔽时钟信号产生屏蔽信号，以及耦合在所述第一和第二单元之间的多路复用器。 描述和要求保护其他实施例。

公开(公告)号：US5920489A

公开(公告)日：1999-07-06

申请号：US642292

申请日：1996-05-03

申请人： Michael T. Dibrino ,  David M. Wu

发明人： Michael T. Dibrino ,  David M. Wu

IPC分类号： G06F11/26 ,  G06F11/267 ,  G06F17/50 ,  G06F9/455

CPC分类号： G06F11/2215 ,  G06F17/5022 ,  G06F11/261

摘要： A method and system for modeling the behavior of a circuit are disclosed. A list specifying a plurality of transistors within the circuit and interconnections between the plurality of transistors is provided. Each fan node within the circuit is identified, where a fan node is defined as a point of interconnection between two or more of the plurality of transistors from which multiple nonredundant current paths to power, ground, or an input of the circuit exist. A fan node equation set is constructed that expresses a logical state of each fan node of the circuit in response to various transistor gate signal states. In addition, an output node equation is constructed that expresses a logical state of an output node of the circuit in terms of selected fan node logical states and specified transistor gate signal states. In response to receipt of a set of states of inputs to the circuit, a logical state of the output node is determined utilizing the fan node equation set and the output equation in order to model behavior of the circuit.

摘要翻译： 公开了一种用于对电路行为进行建模的方法和系统。 提供了指定电路内的多个晶体管和多个晶体管之间的互连的列表。 识别电路内的每个风扇节点，其中风扇节点被定义为多个晶体管中的两个或更多个晶体管之间的互连点，从该多个晶体管的多个非冗余电流路径到达电源，地或电路的输入。 构造了响应于各种晶体管栅极信号状态来表示电路的每个风扇节点的逻辑状态的风扇节点方程组。 另外，根据所选择的风扇节点逻辑状态和指定的晶体管栅极信号状态，构造输出节点方程，其表示电路的输出节点的逻辑状态。 响应于接收到电路的一组输入状态，使用风扇节点方程组和输出方程来确定输出节点的逻辑状态，以便模拟电路的行为。

公开(公告)号：US06795948B2

公开(公告)日：2004-09-21

申请号：US09750200

申请日：2000-12-27

申请人： Chih-Jen Lin ,  David M. Wu

发明人： Chih-Jen Lin ,  David M. Wu

IPC分类号： G06F1750

CPC分类号： G01R31/318385 ,  G01R31/318547

摘要： An apparatus and method of testing an integrated circuit by downloading a sequence of randomly weighted bits into a scan chain in which each bit has a distinctly determined weight generated in real-time by a weight generator. The weight generator has a switch controlled by a stored bit particular for each bit of the randomly weighted bits that determines the weight of the bit. The control signal is stored in a memory that is downloaded into the switch in synchronization with the generation of the bit. Preferably, the memory is on-die, and furthermore is a part of the integrated circuit.

摘要翻译： 通过将随机加权比特序列下载到扫描链中来测试集成电路的装置和方法，其中每个比特具有由权重发生器实时生成的明确确定的权重。 权重发生器具有由随机加权比特的每个比特特定的存储位控制的开关，其确定比特的权重。 控制信号与位的生成同步地存储在下载到开关中的存储器中。 优选地，存储器是裸片上的，此外是集成电路的一部分。

公开(公告)号：US5581699A

公开(公告)日：1996-12-03

申请号：US441571

申请日：1995-05-15

申请人： Humberto F. Casal ,  Hehching H. Li ,  David M. Wu

发明人： Humberto F. Casal ,  Hehching H. Li ,  David M. Wu

IPC分类号： G01R31/30 ,  G01R31/317 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31727 ,  G01R31/30

摘要： The present invention utilizes a test circuit for receiving a reference clock signal and a sense clock signal and subsequently determining whether or not the reference and sense clock signals are either correct multiples of each other and/or in phase with each other. The test circuit may be located on the same chip with the microprocessor and the clock circuitry. The clock circuitry may include a phase locked loop ("PLL") circuit for receiving the reference clock signal and producing a sense clock signal for use by the remainder of the chip, wherein the sense clock signal is a multiple of the reference clock signal. The test circuit may count the number of cycles of the sense clock signal occurring within a predetermined amount of time, which may be proportional to the reference clock period. Alternatively, the sense clock signal and the reference clock signal may be passed through an XOR circuit and then the number of cycles counted within a predetermined time period. In both cases, if the number of cycles counted is not what was expected, then it is known that the sense clock signal was not properly produced by the PLL circuit.

摘要翻译： 本发明利用测试电路来接收参考时钟信号和感测时钟信号，随后确定参考和感测时钟信号是否是彼此的正确倍数和/或彼此同相。 测试电路可以与微处理器和时钟电路位于同一芯片上。 时钟电路可以包括锁相环（“PLL”）电路，用于接收参考时钟信号并产生用于由芯片的其余部分使用的感测时钟信号，其中感测时钟信号是参考时钟信号的倍数。 测试电路可以计数在预定时间量内发生的感测时钟信号的周期数，其可以与参考时钟周期成比例。 或者，感测时钟信号和参考时钟信号可以通过XOR电路，然后在预定时间段内计数周期数。 在这两种情况下，如果计数的周期数不是预期的，则知道感测时钟信号没有被PLL电路正确地产生。

公开(公告)号：US5042034A

公开(公告)日：1991-08-20

申请号：US427549

申请日：1989-10-27

申请人： Anthony Correale, Jr. ,  Richard M. Doney ,  Kim E. O'Donnell ,  Andrew Kegl ,  Erwin A. Tate ,  David M. Wu

发明人： Anthony Correale, Jr. ,  Richard M. Doney ,  Kim E. O'Donnell ,  Andrew Kegl ,  Erwin A. Tate ,  David M. Wu

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC分类号： G01R31/318572

摘要： The present invention implements self testable boundary logic by using a tristate pass gate and a tristate receiver in combination with a linear feedback shift register, a storage register, and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.