公开(公告)号：US07216274B2

公开(公告)日：2007-05-08

申请号：US10609254

申请日：2003-06-26

申请人： Talal K. Jaber ,  Srinivas Patil ,  Larry E. Thatcher ,  Chih-Jen M. Lin ,  Anil K. Sabbavarapu ,  David M. Wu ,  Madhukar K. Reddy

发明人： Talal K. Jaber ,  Srinivas Patil ,  Larry E. Thatcher ,  Chih-Jen M. Lin ,  Anil K. Sabbavarapu ,  David M. Wu ,  Madhukar K. Reddy

IPC分类号： G01R31/28

CPC分类号： G01R31/318552 ,  G01R31/318594 ,  G06F11/2236

摘要： A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

摘要翻译： 用于测试复杂集成电路的测试架构，其中每个功能单元可以独立于其他功能单元进行测试。 本发明的实施例允许功能单元的测试以比处理器的其它部分更慢或更快的时钟速度发生，而不会引起延迟或其他不利的定时效应。

公开(公告)号：US08793095B2

公开(公告)日：2014-07-29

申请号：US13044272

申请日：2011-03-09

申请人： Srinivas Patil ,  Abhijit Jas ,  Peter Lisherness ,  Enrico Carrieri

发明人： Srinivas Patil ,  Abhijit Jas ,  Peter Lisherness ,  Enrico Carrieri

IPC分类号： G01R31/00 ,  G06F11/00

CPC分类号： G06F11/267 ,  G01R31/318508

摘要： A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. The TAM may be implemented in a fabric-to-fabric bridge, enabling testing of IP blocks connected to fabrics on both sides of the bridge.

摘要翻译： 一种测试访问机制（TAM）体系结构，用于促进集成在片上系统（SoC）上的IP块的测试。 TAM架构包括一个测试控制器和一个或多个集成在靠近IP模块的SoC上的测试包装器。 与外部测试仪的输入相对应的测试数据和命令由测试控制器打包，并通过互连结构发送到测试包装机。 测试包装器采用与一个或多个测试端口的接口来向IP块提供测试数据，控制和/或激励信号，以便于IP块的电路级测试。 电路级测试的测试结果通过结构返回测试控制器。 测试包装器可以被配置为通过互连信号，从而通过测试包和通过该结构在测试控制器和IP块之间传输的测试结果来促进IP块的功能测试。 TAM可以在Fabric-to-fabric桥中实现，从而能够测试连接到网桥两侧的Fabric的IP块。

公开(公告)号：US07861116B2

公开(公告)日：2010-12-28

申请号：US11967674

申请日：2007-12-31

申请人： Abhijit Jas ,  Srinivas Patil ,  Rajesh Galivanche ,  Ramtilak Vemu

发明人： Abhijit Jas ,  Srinivas Patil ,  Rajesh Galivanche ,  Ramtilak Vemu

IPC分类号： G06F11/00

CPC分类号： G06F17/5022 ,  G06F11/261 ,  G06F2217/10

摘要： A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.

摘要翻译： 一种用于接受预先指定用于检测电路部分中的错误的多个用户选择的属性的方法，装置和系统，接受多个用户选择的错误输出，每个可以对应于多个用户选择的错误输出中的一个， 所选择的一组属性，对所述多个用户选择的属性中的每一个执行所述电路的模拟，在所述模拟的输出中检测所述多个用户选择的所述多个用户选择的错误输出中的一个， 的用户选择的属性，并且对所述多个用户选择的属性中的对应的一个进行对所述电路的纠错。 一种用于自动选择一组输入的子集的方法，装置和系统，其在输入到电路模拟中时产生错误的输出数据到电路的主输出并且对其进行电路的纠错。 描述和要求保护其他实施例。

公开(公告)号：US20120233504A1

公开(公告)日：2012-09-13

申请号：US13044257

申请日：2011-03-09

申请人： Srinivas Patil ,  Abhijit Jas

发明人： Srinivas Patil ,  Abhijit Jas

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  G06F11/2242 ,  G06F11/3656

摘要： A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

摘要翻译： 一种测试访问机制（TAM）体系结构，用于促进集成在片上系统（SoC）上的IP块的测试。 TAM架构包括一个测试控制器和一个或多个集成在靠近IP模块的SoC上的测试包装器。 与外部测试仪的输入相对应的测试数据和命令由测试控制器打包，并通过互连结构发送到测试包装机。 测试包装器采用一个或多个测试端口向IP块提供测试数据，控制和/或激励信号，以便于IP块的电路级测试。 电路级测试的测试结果通过结构返回测试控制器。 测试包装器可以被配置为通过互连信号，从而通过测试包和通过该结构在测试控制器和IP块之间传输的测试结果来促进IP块的功能测试。

公开(公告)号：US07155648B2

公开(公告)日：2006-12-26

申请号：US10666169

申请日：2003-09-19

申请人： Abhijit Jas ,  Srinivas Patil

发明人： Abhijit Jas ,  Srinivas Patil

IPC分类号： G01R31/3177 ,  G01R31/3187

CPC分类号： G06F11/263 ,  G01R31/318547 ,  G01R31/318566

摘要： An apparatus has an integrated circuit that includes a seed register, a linear feedback shift register to load a test vector into a number of scan chains, and a signature register to receive a test response from the scan chains. The seed register, the linear feedback shift register, and the signature register each have the same register length. The linear feedback shift register and the signature register have the same shift frequency that is greater than a frequency at which a seed vector is loaded into the seed register. The linear feedback shift register is adapted to be selectively provided with bits to control a degree to which its vector is dependent on previous vectors. The scan chains may be configured as a single group providing a test response to a single input signature register or a set of groups providing a test response to a multiple input signature register.

摘要翻译： 一种装置具有集成电路，其包括种子寄存器，用于将测试矢量加载到多个扫描链中的线性反馈移位寄存器，以及用于从扫描链接收测试响应的签名寄存器。 种子寄存器，线性反馈移位寄存器和签名寄存器各自具有相同的寄存器长度。 线性反馈移位寄存器和签名寄存器具有与将种子向量加载到种子寄存器中的频率相同的移位频率。 线性反馈移位寄存器适于选择性地提供位以控制其向量依赖于先前向量的程度。 扫描链可以被配置为向单个输入签名寄存器或提供对多输入签名寄存器的测试响应的一组组提供测试响应的单个组。

公开(公告)号：US5912900A

公开(公告)日：1999-06-15

申请号：US767244

申请日：1996-12-13

申请人： Christopher McCall Durham ,  Peter Juergen Klim ,  Srinivas Patil

发明人： Christopher McCall Durham ,  Peter Juergen Klim ,  Srinivas Patil

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318536

摘要： From a first circuit, information is output in response to acknowledgement signals. From a second circuit, the acknowledgement signals are output in response to the second circuit receiving portions of the information from the first circuit. The portions and the acknowledgement signals are output asynchronously with respect to one another. With at least one of the first and second circuits, a signal having a logic state is received, the logic state is latched, and an operation is performed in response to the latched logic state.

摘要翻译： 从第一电路，响应于确认信号输出信息。 响应于第二电路接收来自第一电路的信息的部分，从第二电路输出确认信号。 部分和确认信号相对于彼此异步地输出。 利用第一和第二电路中的至少一个，接收到具有逻辑状态的信号，锁存逻辑状态，并且响应于锁存的逻辑状态执行操作。

公开(公告)号：US5870411A

公开(公告)日：1999-02-09

申请号：US767243

申请日：1996-12-13

申请人： Christopher McCall Durham ,  Peter Juergen Klim ,  Srinivas Patil

发明人： Christopher McCall Durham ,  Peter Juergen Klim ,  Srinivas Patil

IPC分类号： G01R31/28

CPC分类号： G01R31/318544

摘要： From a first circuit, first information is output in response to acknowledgement signals. From a second circuit, second information and the acknowledgement signals are output. The second information and the acknowledgement signals are output in response to the second circuit receiving portions of the first information from the first circuit during a functional mode of operation. The portions and the acknowledgement signals are output asynchronously with respect to one another. From a third circuit, third information is output in response to the second information. From a test circuit, the second information output from the second circuit is specified, so that the third circuit outputs the third information in response to the specified second information independent of the first information output from the first circuit during a test mode of operation.

摘要翻译： 从第一电路，响应于确认信号输出第一信息。 从第二电路输出第二信息和确认信号。 第二信息和确认信号在功能操作模式期间响应于第二电路接收来自第一电路的第一信息的部分而被输出。 部分和确认信号相对于彼此异步地输出。 从第三电路，响应于第二信息输出第三信息。 从测试电路，指定从第二电路输出的第二信息，使得第三电路在测试操作模式期间响应于指定的第二信息输出与第一电路输出的第一信息无关的第三信息。

公开(公告)号：US08522189B2

公开(公告)日：2013-08-27

申请号：US13044257

申请日：2011-03-09

申请人： Srinivas Patil ,  Abhijit Jas

发明人： Srinivas Patil ,  Abhijit Jas

IPC分类号： G06F17/50

CPC分类号： G06F11/263 ,  G06F11/2242 ,  G06F11/3656

摘要： A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

公开(公告)号：US20070168767A1

公开(公告)日：2007-07-19

申请号：US11520203

申请日：2006-09-12

申请人： Talal Jaber ,  Srinivas Patil ,  Larry Thatcher ,  Chih-Jen Lin ,  Anil Sabbavarapu ,  David Wu ,  Madhukar Reddy

发明人： Talal Jaber ,  Srinivas Patil ,  Larry Thatcher ,  Chih-Jen Lin ,  Anil Sabbavarapu ,  David Wu ,  Madhukar Reddy

IPC分类号： G11B20/20 ,  G06K5/04 ,  G11B5/00

CPC分类号： G01R31/318552 ,  G01R31/318594 ,  G06F11/2236

摘要： A testing architecture for testing a complex integrated circuit in which each functional unit may be tested independently of the others. Embodiments of the invention allow testing of functional units to take place at slower or faster clock speeds than other portions of the processor without incurring delay or other adverse timing effects.

公开(公告)号：US07197721B2

公开(公告)日：2007-03-27

申请号：US10321074

申请日：2002-12-17

申请人： Srinivas Patil ,  Sandip Kundu

发明人： Srinivas Patil ,  Sandip Kundu

IPC分类号： G06F17/50

CPC分类号： G06F11/2733 ,  G01R31/31921 ,  H03M7/46

摘要： According to some embodiments, provided are a pseudo-random sequence generator to generate a pseudo-random sequence of data values, a decoder to receive compressed weight values and to generate decompressed weight values, and a weighting unit to receive the pseudo-random sequence of data values, to receive the decompressed weight values and to weight the pseudo-random sequence of data values based on the decompressed weight values.

摘要翻译： 根据一些实施例，提供了一种用于产生数据值的伪随机序列的伪随机序列发生器，用于接收压缩权重值并生成解压缩权重值的解码器，以及加权单元，用于接收伪随机序列的伪随机序列 数据值，以接收解压缩权重值，并且基于解压缩权重值对数据值的伪随机序列加权。