公开(公告)号：US5241493A

公开(公告)日：1993-08-31

申请号：US807697

申请日：1991-12-16

申请人： Tan V. Chu ,  Faraydon O. Karim ,  Christopher H. Olson

发明人： Tan V. Chu ,  Faraydon O. Karim ,  Christopher H. Olson

IPC分类号： G06F7/487 ,  G06F7/527 ,  G06F7/533 ,  G06F7/544

CPC分类号： G06F7/5443 ,  G06F2207/386 ,  G06F2207/3884 ,  G06F7/483

摘要： An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

公开(公告)号：US5442766A

公开(公告)日：1995-08-15

申请号：US959194

申请日：1992-10-09

申请人： Tan V. Chu ,  Charles R. Moore ,  John S. Muhich ,  Terence M. Potter

发明人： Tan V. Chu ,  Charles R. Moore ,  John S. Muhich ,  Terence M. Potter

IPC分类号： G06F9/38 ,  G06F12/10 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F9/3863 ,  G06F12/1027 ,  G06F2212/682

摘要： A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions to the processor units. A memory management unit (MMU) is established which includes a translation buffer and translation algorithms for implementing page table and address block type translations of every effective address within the data processing system into real addresses within memory. A translation array, which includes a small number of translation objects for translating effective addresses into real addresses, is then established within the fetcher unit. The translation objects are periodically and selectively varied, utilizing the translation capability of the memory management unit (MMU), in response to a failure to translate an effective address into a real address within the fetcher unit. A translation object within the translation array is preferably replaced each time the fetcher unit fails to translate an effective address into a real address by replacing the least recently utilized (LRU) translation object with a newly determined translation object. In the event of a predicted conditional branch instruction, the utilization status (LRU) is temporarily stored and thereafter utilized to restore the translation array to its previous (LRU) state if the predicted conditional branch is resolved as incorrect. In this manner, the least recently utilized (LRU) state of the translation array will not be corrupted by incorrect path predictions.

摘要翻译： 一种用于分布式指令地址转换的方法和系统，具有多个处理器单元，用于执行存储在存储器中的实际地址中的多个任务，指令和数据的多级数据处理系统以及用于将指令读取和分派到处理器单元的提取器单元。 建立了存储器管理单元（MMU），其包括翻译缓冲器和翻译算法，用于将数据处理系统内的每个有效地址的页表和地址块类型转换实现为存储器内的实际地址。 然后，在提取器单元内建立包括少量用于将有效地址转换为实际地址的翻译对象的翻译数组。 响应于将有效地址转换为提取器单元内的实际地址的故障，利用存储器管理单元（MMU）的转换能力周期性地选择性地改变翻译对象。 翻译数组中的翻译对象优选地在每当通过用新确定的翻译对象替换最近最少使用的（LRU）翻译对象时，无效地将有效地址转换成实地址时被替换。 在预测条件分支指令的情况下，如果预测的条件分支被解析为不正确，则利用状态（LRU）被临时存储，并且此后被用于将转换数组恢复到其先前的（LRU）状态。 以这种方式，翻译数组的最近最少利用（LRU）状态不会被不正确的路径预测所破坏。